公开(公告)号：US11605777B2

公开(公告)日：2023-03-14

申请号：US17006923

申请日：2020-08-31

申请人： UNITED MICROELECTRONICS CORP.

发明人： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC分类号： H01L43/02 ,  H01L43/12 ,  H01L27/22

摘要： An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile stress pieces.

公开(公告)号：US20240332087A1

公开(公告)日：2024-10-03

申请号：US18739286

申请日：2024-06-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

摘要： A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US20230005795A1

公开(公告)日：2023-01-05

申请号：US17393387

申请日：2021-08-03

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/423

摘要： A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US20240332086A1

公开(公告)日：2024-10-03

申请号：US18739261

申请日：2024-06-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

摘要： A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US12016250B2

公开(公告)日：2024-06-18

申请号：US17725511

申请日：2022-04-20

申请人： UNITED MICROELECTRONICS CORP.

发明人： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC分类号： H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC分类号： H10N50/80 ,  H10B61/00 ,  H10N50/01

摘要： An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

公开(公告)号：US12040234B2

公开(公告)日：2024-07-16

申请号：US17393387

申请日：2021-08-03

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

摘要： A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US20220246839A1

公开(公告)日：2022-08-04

申请号：US17725511

申请日：2022-04-20

申请人： UNITED MICROELECTRONICS CORP.

发明人： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC分类号： H01L43/02 ,  H01L43/12 ,  H01L27/22

摘要： An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.