公开(公告)号：US20230163184A1

公开(公告)日：2023-05-25

申请号：US17752888

申请日：2022-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Purakh Raj Verma ,  Rudy Octavius Sihombing ,  Shyam Parthasarathy ,  JINYU LIAO

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L29/41758 ,  H01L29/0653 ,  H01L21/823418 ,  H01L21/823481

Abstract: A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.

公开(公告)号：US20220270973A1

公开(公告)日：2022-08-25

申请号：US17204966

申请日：2021-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Su Xing ,  Shyam Parthasarathy

IPC: H01L23/538 ,  H01L25/065 ,  H01L27/06 ,  H01L23/552 ,  H01L21/50 ,  H01L21/768

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device wafer includes a first insulating layer, a first device layer on the first insulating layer, and a first bonding layer on the first device layer. The second device wafer includes a second insulating layer, a second device layer on a first side of the second insulating layer, and a second bonding layer on the second device layer. The second device layer includes a second device region and a second transistor in the second device region. The second device wafer is bonded to the first device wafer by bonding the second bonding layer with the first bonding layer. A shielding structure is on a second side of the second insulating layer opposite to the first side and vertically overlapped with the second device region.

公开(公告)号：US20250072092A1

公开(公告)日：2025-02-27

申请号：US18948563

申请日：2024-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Purakh Raj Verma ,  Rudy Octavius Sihombing ,  Shyam Parthasarathy ,  Jinyu Liao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417

Abstract: A method of manufacturing a multi-finger transistor structure is provided in the present invention, including forming shallow trench isolations in a substrate to define multiple active areas, forming a gate structure on the substrate, wherein the gate structure includes multiple gate parts and multiple connecting parts, and each gate part traverses over one of the active area, and each connecting part alternatively connect one end and the other end of two adjacent gate parts, so as to form meander gate structure.

公开(公告)号：US12191367B2

公开(公告)日：2025-01-07

申请号：US17752888

申请日：2022-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Purakh Raj Verma ,  Rudy Octavius Sihombing ,  Shyam Parthasarathy ,  Jinyu Liao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417

Abstract: A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.