公开(公告)号：US20150004732A1

公开(公告)日：2015-01-01

申请号：US14489495

申请日：2014-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bang-Chiang Lan ,  Li-Hsun Ho ,  Wei-Cheng Wu ,  Hui-Min Wu ,  Min Chen ,  Tzung-I Su ,  Chien-Hsin Huang

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0742 ,  B81C2203/0792 ,  H01L27/0688

Abstract: A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.

Abstract translation: 制造用于MEMS器件和半导体器件的集成结构的方法包括以下步骤：在半导体器件区域中提供其上具有晶体管的衬底及其中的MEMS区域中的第一MEMS部件; 在所述半导体器件区域中的所述衬底上执行互连处理，以形成多个第一电介质层，所述第一介电层中的至少导电插塞和至少导电层; 在蚀刻停止装置区域中在衬底上的第二介电层中形成多个第二电介质层和蚀刻停止装置; 在MEMS区域中的衬底上的第三电介质层中形成多个第三电介质层和至少第二MEMS部件; 并执行蚀刻工艺以去除MEMS区域中的第三介电层。

公开(公告)号：US09988264B2

公开(公告)日：2018-06-05

申请号：US14489495

申请日：2014-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bang-Chiang Lan ,  Li-Hsun Ho ,  Wei-Cheng Wu ,  Hui-Min Wu ,  Min Chen ,  Tzung-I Su ,  Chien-Hsin Huang

IPC: H01L21/00 ,  B81C1/00 ,  H01L27/06

CPC classification number: B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0742 ,  B81C2203/0792 ,  H01L27/0688

Abstract: A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.