公开(公告)号：US20170047427A1

公开(公告)日：2017-02-16

申请号：US15339942

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yin-Cheng Cheng ,  Po-Lun Cheng ,  Ming-Chih Hsu ,  Ya-Chen Chang ,  Hsien-Yao Chu

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer. Preferably, the step of forming the epitaxial layer further includes: forming a buffer layer in the substrate; forming a bulk layer on the buffer layer; forming a linear gradient cap on the bulk layer, and forming a silicon cap on the linear gradient cap. Preferably, the etching to deposition ratio of the linear gradient cap is greater than 50% and less than 100%.

Abstract translation: 公开了半导体器件的制造方法。 首先，提供衬底，在衬底上形成栅极结构，在栅极结构周围形成间隔物，并且在与衬垫相邻的衬底中形成外延层。 优选地，形成外延层的步骤还包括：在衬底中形成缓冲层; 在缓冲层上形成体层; 在本体层上形成线性梯度盖，并在线性梯度盖上形成硅帽。 优选地，线性梯度盖的蚀刻到沉积比率大于50％且小于100％。

公开(公告)号：US09761693B2

公开(公告)日：2017-09-12

申请号：US15339942

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yin-Cheng Cheng ,  Po-Lun Cheng ,  Ming-Chih Hsu ,  Ya-Chen Chang ,  Hsien-Yao Chu

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer. Preferably, the step of forming the epitaxial layer further includes: forming a buffer layer in the substrate; forming a bulk layer on the buffer layer; forming a linear gradient cap on the bulk layer, and forming a silicon cap on the linear gradient cap. Preferably, the etching to deposition ratio of the linear gradient cap is greater than 50% and less than 100%.

公开(公告)号：US20160155818A1

公开(公告)日：2016-06-02

申请号：US14555597

申请日：2014-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yin-Cheng Cheng ,  Po-Lun Cheng ,  Ming-Chih Hsu ,  Ya-Chen Chang ,  Hsien-Yao Chu

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; and forming an epitaxial layer on the substrate, in which an etching to deposition ratio of the epitaxial layer is greater than 50%.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 以及在所述衬底上形成外延层，其中所述外延层的蚀刻到沉积比率大于50％。