公开(公告)号：US20160196971A1

公开(公告)日：2016-07-07

申请号：US14588975

申请日：2015-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Han-Lin Hsu ,  Po-Lun Cheng ,  Chun-Liang Chen ,  Meng-Che Yeh ,  Shih-Jung Tu

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66477 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659

Abstract: A method of forming a gate dielectric layer for a MOS transistor includes the following steps. A gate dielectric layer is formed on a substrate. A nitrdation process is performed on the gate dielectric layer. A multi-step post nitridation annealing process including two oxygen-containing annealing steps with different respective annealing temperatures is performed on the gate dielectric layer.

Abstract translation: 形成用于MOS晶体管的栅介质层的方法包括以下步骤。 在基板上形成栅极电介质层。 在栅介质层上进行氮化处理。 在栅介质层上进行包括具有不同退火温度的两个含氧退火步骤的多步氮化退火工艺。

公开(公告)号：US20170207079A1

公开(公告)日：2017-07-20

申请号：US14996238

申请日：2016-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Lee ,  Kuo-Wei Chih ,  Chen-Hsu Hung ,  Chun-Li Lin ,  Chia-Yen Hsu ,  Tsung-Hsun Tsai ,  Po-Lun Cheng

IPC: H01L21/02 ,  B08B3/08 ,  B08B3/02

CPC classification number: H01L21/02057 ,  B08B3/10 ,  H01L21/67051

Abstract: A substrate cleaning method is provided. A substrate is provided, followed by performing a first pre-cleaning process with a first rotation speed and a first duration time. After the first pre-cleaning process, a second pre-cleaning process is performed with a second rotation speed and a second duration time, wherein the second rotation speed is greater than the first rotation speed. After the second pre-cleaning process, a cleaning process is performed by using a chemical agent with a cleaning rotation speed.

公开(公告)号：US09761687B2

公开(公告)日：2017-09-12

申请号：US14588975

申请日：2015-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Han-Lin Hsu ,  Po-Lun Cheng ,  Chun-Liang Chen ,  Meng-Che Yeh ,  Shih-Jung Tu

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L29/02 ,  H01L21/02

CPC classification number: H01L29/66477 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659

Abstract: A method of forming a gate dielectric layer for a MOS transistor includes the following steps. A gate dielectric layer is formed on a substrate. A nitridation process is performed on the gate dielectric layer. A multi-step post nitridation annealing process including two oxygen-containing annealing steps with different respective annealing temperatures is performed on the gate dielectric layer.

公开(公告)号：US20170186607A1

公开(公告)日：2017-06-29

申请号：US14981854

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Kuo ,  Shih-Jung Tu ,  Chun-Liang Chen ,  Po-Lun Cheng

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/3205

CPC classification number: H01L21/28202 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: The method of forming a semiconductor device is provided. A substrate having an exposed oxide layer is provided. A nitridation process is performed for the oxide layer. After the nitridation process, a plasma treatment containing an inert gas is performed for the oxide layer. A conductive layer is formed on the oxide layer.

公开(公告)号：US20170098558A1

公开(公告)日：2017-04-06

申请号：US14935210

申请日：2015-11-06

Applicant: United Microelectronics Corp.

Inventor： Tzung-Wu Hou ,  Po-Lun Cheng ,  Meng-Che Yeh ,  Feng-Nan Chu

IPC: H01L21/67 ,  C09K13/04 ,  C09K13/08

CPC classification number: H01L21/67086 ,  H01L21/31111 ,  H01L21/67057 ,  H01L21/67075 ,  Y10T137/7287

Abstract: An acid replenishing system includes an acid tank, a draining apparatus, an acid replenishing apparatus, and a control unit. The acid tank contains a used acid solution. The draining apparatus drains an amount of the used acid solution from the acid tank. The acid replenishing apparatus replenishes an amount of a replenishing acid into the acid tank. The control unit controls the draining apparatus and the acid replenishing apparatus to perform a plurality of acid replenishing stages, so a total set amount of the replenishing acid to be added into the acid tank has been replenished.

公开(公告)号：US20170047427A1

公开(公告)日：2017-02-16

申请号：US15339942

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yin-Cheng Cheng ,  Po-Lun Cheng ,  Ming-Chih Hsu ,  Ya-Chen Chang ,  Hsien-Yao Chu

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer. Preferably, the step of forming the epitaxial layer further includes: forming a buffer layer in the substrate; forming a bulk layer on the buffer layer; forming a linear gradient cap on the bulk layer, and forming a silicon cap on the linear gradient cap. Preferably, the etching to deposition ratio of the linear gradient cap is greater than 50% and less than 100%.

Abstract translation: 公开了半导体器件的制造方法。 首先，提供衬底，在衬底上形成栅极结构，在栅极结构周围形成间隔物，并且在与衬垫相邻的衬底中形成外延层。 优选地，形成外延层的步骤还包括：在衬底中形成缓冲层; 在缓冲层上形成体层; 在本体层上形成线性梯度盖，并在线性梯度盖上形成硅帽。 优选地，线性梯度盖的蚀刻到沉积比率大于50％且小于100％。

公开(公告)号：US09761693B2

公开(公告)日：2017-09-12

申请号：US15339942

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yin-Cheng Cheng ,  Po-Lun Cheng ,  Ming-Chih Hsu ,  Ya-Chen Chang ,  Hsien-Yao Chu

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer. Preferably, the step of forming the epitaxial layer further includes: forming a buffer layer in the substrate; forming a bulk layer on the buffer layer; forming a linear gradient cap on the bulk layer, and forming a silicon cap on the linear gradient cap. Preferably, the etching to deposition ratio of the linear gradient cap is greater than 50% and less than 100%.

公开(公告)号：US20160155818A1

公开(公告)日：2016-06-02

申请号：US14555597

申请日：2014-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yin-Cheng Cheng ,  Po-Lun Cheng ,  Ming-Chih Hsu ,  Ya-Chen Chang ,  Hsien-Yao Chu

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; and forming an epitaxial layer on the substrate, in which an etching to deposition ratio of the epitaxial layer is greater than 50%.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 以及在所述衬底上形成外延层，其中所述外延层的蚀刻到沉积比率大于50％。