公开(公告)号：US20200279917A1

公开(公告)日：2020-09-03

申请号：US16878542

申请日：2020-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Che-Hsien Lin ,  Cheng-Yeh Huang ,  Chun-Jen Huang ,  Yu-Chih Su ,  Yao-Jhan Wang

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

公开(公告)号：US20190148550A1

公开(公告)日：2019-05-16

申请号：US16244076

申请日：2019-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US10446682B2

公开(公告)日：2019-10-15

申请号：US16244076

申请日：2019-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US10283415B2

公开(公告)日：2019-05-07

申请号：US16132460

申请日：2018-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  An-Chi Liu ,  Nan-Yuan Huang ,  Yu-Chih Su ,  Cheng-Pu Chiu ,  Tien-Shan Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.

公开(公告)号：US10211107B1

公开(公告)日：2019-02-19

申请号：US15700175

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Yu-Chih Su ,  Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Te-Chang Hsu ,  Chin-Yang Hsieh ,  An-Chi Liu ,  Kuan-Lin Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762

Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.

公开(公告)号：US10109531B1

公开(公告)日：2018-10-23

申请号：US15616936

申请日：2017-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  An-Chi Liu ,  Nan-Yuan Huang ,  Yu-Chih Su ,  Cheng-Pu Chiu ,  Tien-Shan Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A topmost portion of the first bump is lower than the base, and a width of the first bump is larger than a width of each of the fin shaped structures.

公开(公告)号：US10700163B2

公开(公告)日：2020-06-30

申请号：US16194379

申请日：2018-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Che-Hsien Lin ,  Cheng-Yeh Huang ,  Chun-Jen Huang ,  Yu-Chih Su ,  Yao-Jhan Wang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/78

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

公开(公告)号：US20190080968A1

公开(公告)日：2019-03-14

申请号：US15700175

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Yu-Chih Su ,  Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Te-Chang Hsu ,  Chin-Yang Hsieh ,  An-Chi Liu ,  Kuan-Lin Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762

Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.

公开(公告)号：US20190027603A1

公开(公告)日：2019-01-24

申请号：US15696201

申请日：2017-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US10957762B2

公开(公告)日：2021-03-23

申请号：US16878542

申请日：2020-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Che-Hsien Lin ,  Cheng-Yeh Huang ,  Chun-Jen Huang ,  Yu-Chih Su ,  Yao-Jhan Wang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.