公开(公告)号：US09627541B2

公开(公告)日：2017-04-18

申请号：US14741464

申请日：2015-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Nan-Yuan Huang ,  Shui-Yen Lu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same.

公开(公告)号：US20170084688A1

公开(公告)日：2017-03-23

申请号：US14884787

申请日：2015-10-16

Applicant: United Microelectronics Corp.

Inventor： Jhen-Cyuan Li ,  Nan-Yuan Huang ,  Shui-Yen Lu

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/76232 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate, having a recess disposed therein, an insulating layer filled in the recess and disposed on a surface of the substrate, and at least one fin structure disposed in the insulating layer, the fin structure consisting of two terminal parts and a central part disposed between two terminal parts. The terminal parts are disposed on the surface of the substrate and directly contact the substrate, and the central part is disposed right above the recess.

公开(公告)号：US09583394B2

公开(公告)日：2017-02-28

申请号：US15293292

申请日：2016-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L21/324 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/308 ,  H01L27/092 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.

Abstract translation: 本发明提供一种半导体结构的形成方法，其特征在于，首先，设置具有第一鳍结构和设置在其上的第二鳍结构的衬底，接着，在所述第一鳍结构和所述第二鳍结构之间形成第一隔离区 鳍结构，与第一隔离区相对地形成第二隔离区，并且在第一鳍结构和第二鳍结构的一侧形成至少外延层，其中外延层具有底表面 所述底表面从所述第一鳍结构延伸到所述第二鳍结构，并且所述底表面低于所述第一隔离区域的底表面和所述第二隔离区域的顶表面，此外，所述外延层具有阶梯状 形侧壁轮廓。

公开(公告)号：US12237398B2

公开(公告)日：2025-02-25

申请号：US17338691

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Fu-Jung Chuang ,  Ya-Yin Hsiao ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

公开(公告)号：US20210296466A1

公开(公告)日：2021-09-23

申请号：US17338691

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Fu-Jung Chuang ,  Ya-Yin Hsiao ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/08 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

公开(公告)号：US20160365344A1

公开(公告)日：2016-12-15

申请号：US14792591

申请日：2015-07-06

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Abstract translation: 本发明提供了一种半导体结构，其包括具有第一鳍结构和设置在其上的第二鳍结构的衬底，位于第一鳍结构和第二鳍结构之间的第一隔离区，与第一鳍结构相对的第二隔离区 并且至少设置在第一鳍片结构和第二鳍片结构侧的外延层。 外延层具有从第一鳍结构延伸到第二鳍结构的底表面，底表面低于第一隔离区的底表面和第二隔离区的顶表面。

公开(公告)号：US09502410B1

公开(公告)日：2016-11-22

申请号：US14792591

申请日：2015-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Abstract translation: 本发明提供了一种半导体结构，其包括具有第一鳍结构和设置在其上的第二鳍结构的衬底，位于第一鳍结构和第二鳍结构之间的第一隔离区，与第一鳍结构相对的第二隔离区 并且至少设置在第一鳍片结构和第二鳍片结构侧的外延层。 外延层具有从第一鳍结构延伸到第二鳍结构的底表面，底表面低于第一隔离区的底表面和第二隔离区的顶表面。

公开(公告)号：US10121881B2

公开(公告)日：2018-11-06

申请号：US15481419

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Yi-Fan Li ,  Kun-Hsin Chen ,  Tong-Jyun Huang ,  Jyh-Shyang Jenq ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/26 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265

Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.

公开(公告)号：US20170179292A1

公开(公告)日：2017-06-22

申请号：US15447134

申请日：2017-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Nan-Yuan Huang ,  Shui-Yen Lu

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a first spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The fin structure includes an upper portion, a concave portion and a lower portion, and the concave portion is disposed between the upper portion and the lower portion. The first spacer structure is disposed on a sidewall of the gate structure. The first spacer structure includes a first spacer and a second spacer, wherein the first spacer is disposed between the second spacer, and a height of the first spacer is different from a height of the second spacer. The source/drain region is disposed in a semiconductor layer at two sides of the first spacer structure.

公开(公告)号：US09653603B1

公开(公告)日：2017-05-16

申请号：US15139305

申请日：2016-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Yi-Fan Li ,  Kun-Hsin Chen ,  Tong-Jyun Huang ,  Jyh-Shyang Jenq ,  Nan-Yuan Huang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26546 ,  H01L29/1054 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a recess in the substrate; forming a buffer layer in the recess; forming an epitaxial layer on the buffer layer; and removing part of the epitaxial layer, part of the buffer layer, and part of the substrate to form fin-shaped structures.