公开(公告)号：US11844291B2

公开(公告)日：2023-12-12

申请号：US17353757

申请日：2021-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan Zhou ,  Xian Feng Du ,  Guoan Du ,  Guohai Zhang

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/24 ,  H10N70/826 ,  H10N70/841

Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

公开(公告)号：US11355389B2

公开(公告)日：2022-06-07

申请号：US17133652

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US12096704B2

公开(公告)日：2024-09-17

申请号：US18383473

申请日：2023-10-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan Zhou ,  Xian Feng Du ,  Guoan Du ,  Guohai Zhang

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/24 ,  H10N70/826 ,  H10N70/841

Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

公开(公告)号：US12040224B2

公开(公告)日：2024-07-16

申请号：US17737011

申请日：2022-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US20250126889A1

公开(公告)日：2025-04-17

申请号：US18505094

申请日：2023-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： YUERAN QIAO ,  Yi Liu ,  Guohai Zhang ,  Genmao Liu ,  Lei Zhu

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78

Abstract: The invention provides a semiconductor structure comprising a silicon-on-insulator (SOI) substrate, which comprises a silicon layer and an insulating layer stacked from bottom to top, a phosphosilicate glass (PGS) on the insulating layer, and a fluorosilicate glass (FSG) on the phosphosilicate glass. The probability of ions infiltrating into the transistor can be reduced and the yield of products can be improved.

公开(公告)号：US20250113605A1

公开(公告)日：2025-04-03

申请号：US18496941

申请日：2023-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wan-Tien Chou ,  Gang Ren ,  Xingxing Chen ,  Ji Feng ,  Guohai Zhang

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/12

Abstract: A method for fabricating a radio-frequency (RF) device includes the steps of first providing a substrate comprising a core region and a non-core region, forming a shallow trench isolation (STI) in the substrate between the core region and the non-core region, forming a first gate oxide layer on the core region and the non-core region, forming a patterned mask on the non-core region and the STI, removing the first gate oxide layer on the core region, and then forming a second gate oxide layer on the core region.

公开(公告)号：US20240332067A1

公开(公告)日：2024-10-03

申请号：US18739344

申请日：2024-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US11201134B2

公开(公告)日：2021-12-14

申请号：US16853714

申请日：2020-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yonghui Gao ,  Yi Liu ,  Guohai Zhang

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/3105

Abstract: A method of manufacturing a semiconductor device includes the following steps. A device wafer having a product-obtaining part and an edge part surrounding the product-obtaining part is provided. A passivation layer is formed to cover the device wafer. A first oxide cap layer is formed to cover the passivation layer. An edge trimming process is performed to polish an edge part of the first oxide cap layer, an edge part of the passivation layer and the edge part of the device wafer. A removing process is performed to remove the first oxide cap layer after the edge trimming process is performed. A second oxide cap layer is formed to cover the first oxide cap layer and the edge part of the device wafer.

公开(公告)号：US11127621B2

公开(公告)日：2021-09-21

申请号：US16673929

申请日：2019-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ji Feng ,  Yunfei Li ,  Guohai Zhang ,  Ching Hwa Tey ,  Jingling Wang

IPC: H01L21/762 ,  H01L21/76 ,  H01L21/311 ,  H01L21/265

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.