公开(公告)号：US10056288B1

公开(公告)日：2018-08-21

申请号：US15672272

申请日：2017-08-08

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Tsuo-Wen Lu ,  Chin-Wei Wu ,  Tien-Chen Chan ,  Ger-Pin Lin ,  Shu-Yen Chan

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L21/764 ,  H01L21/02

CPC分类号： H01L21/76237 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/764 ,  H01L21/823481 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236

摘要： A semiconductor device includes a semiconductor substrate having a gate trench penetrating through an active area and a trench isolation region surrounding the active area. The gate trench exposes a sidewall of the active area and a sidewall of the trench isolation region. The sidewall of the trench isolation region includes a void. A first gate dielectric layer conformally covers the sidewall of the active area and the sidewall of the trench isolation region. The void in the sidewall of the trench isolation region is filled with the first gate dielectric layer. A second gate dielectric layer is grown on the sidewall of the active area. A gate is embedded in the gate trench.

公开(公告)号：US20190013204A1

公开(公告)日：2019-01-10

申请号：US15659653

申请日：2017-07-26

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Tien-Chen Chan ,  Ger-Pin Lin ,  Tsuo-Wen Lu ,  Chin-Wei Wu ,  Yu-Chun Wang ,  Shu-Yen Chan

IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/74 ,  H01L23/535 ,  H01L29/78

摘要： A method of fabricating a buried word line includes forming a trench in a substrate. Next, a deposition process is performed to form a silicon layer on a sidewall and a bottom at the inner side of the trench. After the deposition process, a gate dielectric layer is formed in the trench. Finally, a conductive layer is formed to fill in the trench.