公开(公告)号：US09378958B2

公开(公告)日：2016-06-28

申请号：US13729034

申请日：2012-12-28

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang

IPC: H01L23/60 ,  H01L21/265 ,  H01L27/02

CPC classification number: H01L21/266 ,  H01L21/265 ,  H01L23/60 ,  H01L27/0277 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.

Abstract translation: 一种制造静电放电保护结构的方法包括以下步骤。 首先，提供半导体衬底。 在半导体衬底中形成多个隔离结构，阱区，第一导电区和第二导电区。 阱区包含第一类导电载体。 第一导电区域和第二导电区域包含第二导电载体。 然后，在半导体衬底的表面上形成掩模层，其中露出第一导电区域的一部分。 然后，通过使用掩模层作为注入掩模，执行第一注入工艺以将第二类型导电载体注入阱区，使得阱区的第一类导电载体的一部分被电中和，并且第一掺杂 区域形成在第一导电区域的暴露部分下方。

公开(公告)号：US08890250B2

公开(公告)日：2014-11-18

申请号：US13729037

申请日：2012-12-28

Applicant: United Microelectronics Corporation

Inventor： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang

IPC: H01L23/62 ,  H01L29/739

CPC classification number: H01L29/0626 ,  H01L29/1083 ,  H01L29/7436 ,  H01L29/7835

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers.

Abstract translation: 静电放电保护结构包括半导体衬底，第一阱区，栅极结构，第二阱区，第二阱区，第二导电区和深阱区。 第一阱区域包含第一类导电载体。 第二阱区域设置在第一阱区域内，并且包含第二类型的导电载体。 第一导电区域设置在第一阱区域的表面上，并且包含第二导电载体。 深阱区域设置在第二阱区域和第一导电区域下方，并与第二阱区域接触。 深井区域包含第二类导电载体。

公开(公告)号：US09627210B2

公开(公告)日：2017-04-18

申请号：US15159816

申请日：2016-05-20

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang

IPC: H01L21/266 ,  H01L21/265 ,  H01L23/60 ,  H01L27/02

CPC classification number: H01L21/266 ,  H01L21/265 ,  H01L23/60 ,  H01L27/0277 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.

公开(公告)号：US09190840B2

公开(公告)日：2015-11-17

申请号：US13956333

申请日：2013-07-31

Applicant: UNITED MICROELECTRONICS CORPORATION ,  National Chiao Tung University

Inventor： Ming-Dou Ker ,  Chun-Yu Lin ,  Chang-Tzu Wang

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0285

Abstract: An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.

Abstract translation: 提供一种适用于包括第一N沟道金属氧化物半导体（NMOS）晶体管的输入级电路的静电放电（ESD）保护电路。 ESD保护电路包括P沟道金属氧化物半导体（PMOS）晶体管和阻抗器件，其中PMOS晶体管具有耦合到第一NMOS晶体管的栅极的源极和耦合到第一NMOS晶体管的源极的漏极 并且阻抗器件耦合在PMOS晶体管的栅极和第一电源轨之间以执行初始ESD保护电路。 由PMOS晶体管和电阻器形成的ESD保护电路能够增加ESD保护电路的接通速度并防止输入级电路从CDM ESD事件发生。

公开(公告)号：US20150129977A1

公开(公告)日：2015-05-14

申请号：US14074727

申请日：2013-11-08

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yu-Chun CHEN ,  Chang-Tzu Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0277

Abstract: A semiconductor electrostatic discharge (ESD) protection apparatus comprises at least one elementary transistor with a first conductivity type, a well region with a second conductivity type, a guard ring with the second conductivity type and a semiconductor interval region. The elementary transistor is formed in the well region. The guard ring surrounds the at least one elementary transistor. The semiconductor interval region is disposed between the elementary transistor and the guard ring in order to surrounds the elementary transistor, wherein the semiconductor interval region is an undoped region, a doped region with the first conductivity type or a doped region with the second conductivity type that has a doping concentration substantially less than that of the well region.

Abstract translation: 半导体静电放电（ESD）保护装置包括至少一个具有第一导电类型的基本晶体管，具有第二导电类型的阱区，具有第二导电类型的保护环和半导体间隔区。 在阱区中形成基本晶体管。 保护环围绕至少一个基本晶体管。 半导体间隔区域设置在基本晶体管和保护环之间以包围基本晶体管，其中半导体间隔区域是未掺杂区域，具有第一导电类型的掺杂区域或具有第二导电类型的掺杂区域， 具有显着小于阱区的掺杂浓度的掺杂浓度。

公开(公告)号：US20130314826A1

公开(公告)日：2013-11-28

申请号：US13956333

申请日：2013-07-31

Applicant: National Chiao Tung University ,  UNITED MICROELECTRONICS CORPORATION

Inventor： Ming-Dou Ker ,  Chun-Yu Lin ,  Chang-Tzu Wang

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0285

Abstract: An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.

Abstract translation: 提供一种适用于包括第一N沟道金属氧化物半导体（NMOS）晶体管的输入级电路的静电放电（ESD）保护电路。 ESD保护电路包括P沟道金属氧化物半导体（PMOS）晶体管和阻抗器件，其中PMOS晶体管具有耦合到第一NMOS晶体管的栅极的源极和耦合到第一NMOS晶体管的源极的漏极 并且阻抗器件耦合在PMOS晶体管的栅极和第一电源轨之间以执行初始ESD保护电路。 由PMOS晶体管和电阻器形成的ESD保护电路能够增加ESD保护电路的接通速度并防止输入级电路从CDM ESD事件发生。