公开(公告)号：US09105355B2

公开(公告)日：2015-08-11

申请号：US13935487

申请日：2013-07-04

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hsin-Wen Chen

IPC: G11C11/41 ,  G11C11/417 ,  G11C11/412 ,  G11C11/413 ,  G11C7/12

CPC classification number: G11C11/417 ,  G11C7/12 ,  G11C11/412 ,  G11C11/413

Abstract: A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first and second memory cells are located in a same column in the memory cell array.

Abstract translation: 存储单元阵列包括位线，互补位线，第一操作电压供给电路，第二操作电压供给电路，第一存储单元和第二存储单元。 第一操作电压供应电路电耦合到位线和互补位线，并用于提供第一操作电压。 第二操作电压供应电路电耦合到位线和互补位线，并用于提供第二操作电压。 第一存储单元电耦合到位线和互补位线，并用于接收第一操作电压。 第二存储单元电耦合到位线和互补位线，并用于接收第二操作电压。 第一和第二存储单元位于存储单元阵列中的同一列中。

公开(公告)号：US08711598B1

公开(公告)日：2014-04-29

申请号：US13682742

申请日：2012-11-21

Applicant: United Microelectronics Corporation

Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Shih-Chin Lin

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G11C8/14 ,  G11C11/418

Abstract: A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.

Abstract translation: 存储单元包括六个晶体管。 第一和第二P型晶体管具有耦合到第一电压的源极。 第一和第二N型晶体管分别具有耦合到第一和第二P型晶体管的漏极的漏极; 所述源耦合到第二电压; 并且分别与第一和第二P型晶体管的栅极耦合的栅极。 第三N型晶体管具有耦合到写字线的漏极; 源极耦合到第一N型晶体管的漏极和第二N型晶体管的栅极; 并且栅极耦合到第一写入位线。 第四N型晶体管具有耦合到写字线的漏极; 所述源极耦合到所述第二N型晶体管的漏极和所述第一N型晶体管的栅极; 并且栅极耦合到第二写入位线。 还提供了存储单元阵列。