公开(公告)号：US11387241B2

公开(公告)日：2022-07-12

申请号：US17027730

申请日：2020-09-22

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Ming-Shing Chen

IPC分类号： H01L27/11521 ,  H01L27/11558 ,  H01L29/66

摘要： A method for fabricating flash memory is provided. A plurality of floating gate structures is formed on a gate dielectric layer in the memory device region of a substrate. The protective spacers are formed on two opposite sidewalls of each floating gate structure. A polysilicon gate structures are formed on the logic device region and a polysilicon control gate structure with an opening are formed on the memory device region to cover two adjacent floating gate structures, wherein the two protective spacers facing each other between two adjacent floating gate structures are exposed by the opening, and then the exposed protective spacer are removed. An ion implantation is performed on the substrate to form a source region between the two adjacent floating gate structures on each cell area. There will be no polysilicon material residue in the memory device region or pitting/undercutting phenomenon in the logic device region.

公开(公告)号：US20160027683A1

公开(公告)日：2016-01-28

申请号：US14457119

申请日：2014-08-12

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Ming-Shing Chen ,  Yu-Ting Wang ,  Ming-Hui Chang

IPC分类号： H01L21/762 ,  H01L21/3105 ,  H01L21/32 ,  H01L29/06

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed.

摘要翻译： 半导体器件中的浅沟槽隔离结构及其制造方法。 该方法包括以下步骤。 衬底上设置衬垫氧化物层和其上的第一图案化的光刻胶层。 在对应于第一图案化光致抗蚀剂层的基板中形成第一沟槽。 第一介电层沉积在第一沟槽和衬底上。 提供第二图案化光致抗蚀剂层以在第一电介质层中形成开口，并且在衬底中形成对应于第二图案化光致抗蚀剂层的第二沟槽。 沉积覆盖衬底中的第一沟槽和第二沟槽的第二介电层以及衬底上的第一介电层。 第二电介质层通过化学机械抛光进行除去直到暴露第一​​介电层。 选择性地去除衬底上的第一介电层。

公开(公告)号：US20220093620A1

公开(公告)日：2022-03-24

申请号：US17027730

申请日：2020-09-22

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Ming-Shing Chen

IPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A method for fabricating flash memory is provided. A plurality of floating gate structures is formed on a gate dielectric layer in the memory device region of a substrate. The protective spacers are formed on two opposite sidewalls of each floating gate structure. A polysilicon gate structures are formed on the logic device region and a polysilicon control gate structure with an opening are formed on the memory device region to cover two adjacent floating gate structures, wherein the two protective spacers facing each other between two adjacent floating gate structures are exposed by the opening, and then the exposed protective spacer are removed. An ion implantation is performed on the substrate to form a source region between the two adjacent floating gate structures on each cell area. There will be no polysilicon material residue in the memory device region or pitting/undercutting phenomenon in the logic device region.

公开(公告)号：US20160086843A1

公开(公告)日：2016-03-24

申请号：US14957585

申请日：2015-12-02

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Ming-Shing Chen ,  Yu-Ting Wang ,  Ming-Hui Chang

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.

摘要翻译： 半导体器件中的浅沟槽隔离结构及其制造方法。 该方法包括以下步骤。 衬底上设置衬垫氧化物层和其上的第一图案化的光刻胶层。 在对应于第一图案化光致抗蚀剂层的基板中形成第一沟槽。 第一介电层沉积在第一沟槽和衬底上。 提供第二图案化光致抗蚀剂层以在第一电介质层中形成开口，并且在衬底中形成对应于第二图案化光致抗蚀剂层的第二沟槽。 沉积第二电介质层以覆盖衬底中的第一沟槽和第二沟槽以及衬底上的第一介电层。 通过化学机械抛光除去第二介电层，直到暴露第一​​介电层。 选择性地去除衬底上的第一介电层。

公开(公告)号：US09478457B2

公开(公告)日：2016-10-25

申请号：US14957585

申请日：2015-12-02

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Ming-Shing Chen ,  Yu-Ting Wang ,  Ming-Hui Chang

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.

摘要翻译： 半导体器件中的浅沟槽隔离结构及其制造方法。 该方法包括以下步骤。 衬底上设置衬垫氧化物层和其上的第一图案化的光刻胶层。 在对应于第一图案化光致抗蚀剂层的基板中形成第一沟槽。 第一介电层沉积在第一沟槽和衬底上。 提供第二图案化光致抗蚀剂层以在第一电介质层中形成开口，并且在衬底中形成对应于第二图案化光致抗蚀剂层的第二沟槽。 沉积第二电介质层以覆盖衬底中的第一沟槽和第二沟槽以及衬底上的第一介电层。 通过化学机械抛光除去第二介电层，直到暴露第一​​介电层。 选择性地去除衬底上的第一介电层。

公开(公告)号：US09236289B1

公开(公告)日：2016-01-12

申请号：US14457119

申请日：2014-08-12

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Ming-Shing Chen ,  Yu-Ting Wang ,  Ming-Hui Chang

IPC分类号： H01L21/8242 ,  H01L21/762 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/32

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed.

摘要翻译： 半导体器件中的浅沟槽隔离结构及其制造方法。 该方法包括以下步骤。 衬底上设置衬垫氧化物层和其上的第一图案化的光刻胶层。 在对应于第一图案化光致抗蚀剂层的基板中形成第一沟槽。 第一介电层沉积在第一沟槽和衬底上。 提供第二图案化光致抗蚀剂层以在第一电介质层中形成开口，并且在衬底中形成对应于第二图案化光致抗蚀剂层的第二沟槽。 沉积覆盖衬底中的第一沟槽和第二沟槽的第二介电层以及衬底上的第一介电层。 第二电介质层通过化学机械抛光进行除去直到暴露第一​​介电层。 选择性地去除衬底上的第一介电层。