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1.
公开(公告)号:US20180198457A1
公开(公告)日:2018-07-12
申请号:US15460219
申请日:2017-03-15
Inventor: Hua FAN , Hadi HEIDARI , Franco MALOBERTI , Dagang LI , Daqian HU , Yuanjun CEN
CPC classification number: H03M1/004 , H03M1/1009 , H03M1/38
Abstract: A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C1-C128; and 4) selecting 64 groups of capacitors from C33 to C96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.
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2.
公开(公告)号:US20190131998A1
公开(公告)日:2019-05-02
申请号:US16114300
申请日:2018-08-28
Inventor: Hua FAN , Jingxuan YANG , Quanyuan FENG , Dagang LI , Daqian HU , Yuanjun CEN , Hadi HEIDARI , Franco MALOBERTI , Jingtao LI , Huaying SU
IPC: H03M1/46
Abstract: A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.
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