Clocked CMOS circuit with at least one CMOS switch
    1.
    发明授权
    Clocked CMOS circuit with at least one CMOS switch 失效
    具有至少一个CMOS开关的时钟CMOS电路

    公开(公告)号:US4801819A

    公开(公告)日:1989-01-31

    申请号:US67571

    申请日:1987-06-29

    摘要: To avoid interference signals caused by overlapping edges of a switching signal for driving p-channel-transistor/n-channel-transistor pairs, a drive circuit contains a first series combination of the current paths of a first p-channel transistor, a first n-switching transistor, and a first n-channel transistor and a second series combination of a second p-channel transistor, a second n-switching transistor and a second n-channel transistor, with the gate of the first p-channel transistor connected to the current-path junction of the second series combination, and the gate of the second p-channel transistor connected to the current-path junction of the first series combination. The switching signal and the inverse thereof are applied to the gates of the first n-channel transistor and the second n-channel transistor, respectively. The gates of the n-switching transistors are presented with the n-clock. The first and second current-path junctions are followed by a first inverter and a second inverter, respectively. If the transistor pair is to be turned on by the L or H level of the switching signal, the gate of the n-channel transistor of the pair is connected to the first current-path junction or the second current-path junction, respectively, and the gate of the p-channel transistor to the output of the first inverter or the second inverter, respectively.

    摘要翻译: 为了避免由用于驱动p沟道晶体管/ n沟道晶体管对的开关信号的重叠边缘引起的干扰信号,驱动电路包含第一p沟道晶体管的电流路径的第一串联组合,第一n沟道晶体管 开关晶体管,以及第一p沟道晶体管和第二n沟道晶体管的第一n沟道晶体管和第二串联组合,其中第一p沟道晶体管的栅极连接到 第二串联组合的电流路径结和与第一串联组合的电流路径结连接的第二p沟道晶体管的栅极。 开关信号及其反相分别被施加到第一n沟道晶体管和第二n沟道晶体管的栅极。 n开关晶体管的栅极呈现n时钟。 第一和第二电流路径结之后分别是第一反相器和第二反相器。 如果要将晶体管对导通开关信号的L或H电平,则该对的n沟道晶体管的栅极分别连接到第一电流路径结或第二电流路径结, 和p沟道晶体管的栅极分别连接到第一反相器或第二反相器的输出端。

    Circuit for checking the coincidence of a data word with a reference
data word
    2.
    发明授权
    Circuit for checking the coincidence of a data word with a reference data word 失效
    用于检查数据字与参考数据字的一致性的电路

    公开(公告)号:US4812809A

    公开(公告)日:1989-03-14

    申请号:US30043

    申请日:1987-03-23

    IPC分类号: G06F7/04 G06F7/02

    CPC分类号: G06F7/02

    摘要: A circuit checks for coincidence of a data word with a reference data word by means of EXOR gates per digit of the two data words, and a non-coincidence is permitted in a number of digits (m). The output signal that appears at the output of the circuit is the result of the current flowing therein, with the sign thereof being indicative of either a coincidence or a non-coincidence. For this purpose, the individual outputs of the EXOR gates serve to activate switch transistors with the aid of which standard currents (i) are caused to flow from the output, via an N-multiple current source, to the zero point of the circuit (ground). On the other hand, via a first P-current mirror, a current mi and, via a second P-current mirror, a current i/2 are fed to the output. By means of the N-multiple current source, the current mi is impressed upon the current input of the first P-current mirror.

    摘要翻译: 电路通过两个数据字的每个数字的EXOR门检查数据字与参考数据字的一致性,并且许多数字(m)允许不一致。 出现在电路输出端的输出信号是电流在其中流动的结果,其符号表示符合或非重合。 为此,EXOR门的各个输出用于激活开关晶体管,借助于哪个标准电流(i)从输出端经由N倍电流源流向电路的零点(i) 地面)。 另一方面,经由第一P电流镜,电流mi和经由第二P电流镜将电流i / 2馈送到输出。 通过N倍电流源,电流mi施加在第一P电流镜的电流输入端上。