公开(公告)号：US07521994B2

公开(公告)日：2009-04-21

申请号：US11903191

申请日：2007-09-20

申请人： Ulrich Theus ,  Juergen Kessel

发明人： Ulrich Theus ,  Juergen Kessel

IPC分类号： H03F3/45

CPC分类号： H03F3/45968 ,  H03F1/486 ,  H03F3/187 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45744 ,  H03F2200/03 ,  H03F2200/36 ,  H03F2203/45138 ,  H03F2203/45212 ,  H03F2203/45241 ,  H03F2203/45366 ,  H03F2203/45632

摘要： A CMOS output stage operates in A/B push-pull mode and is driven with a control potential (ud) from a preamplifier stage via a control line (st). The control line (st) feeds the gate terminals of a complementary transistor pair (kt), the first transistor (n1) of which is used as first push-pull output transistor and the second transistor (p1) of which is connected to the gate terminal of a second push-pull output transistor (pa) via a current balancing arrangement. The source terminal of the first and of the second transistor (n1, p1) is connected to a first and, respectively, to a second fixed potential (u1, u2), the second fixed potential (u2) being stabilised in a low-impedance manner by an active compensation circuit (K).

摘要翻译： CMOS输出级以A / B推挽模式工作，并通过控制线（st）从前置放大器级的控制电位（ud）驱动。 控制线（st）馈送互补晶体管对（kt）的栅极端子，其第一晶体管（n1）用作第一推挽输出晶体管，第二晶体管（p1）连接到栅极 通过电流平衡装置的第二推挽输出晶体管（pa）的端子。 第一和第二晶体管（n1，p1）的源极端子连接到第一和第二固定电位（u1，u2），第二固定电位（u2）稳定在低阻抗 方式通过有源补偿电路（K）。

公开(公告)号：US06501322B1

公开(公告)日：2002-12-31

申请号：US09611599

申请日：2000-07-07

申请人： Reiner Bidenbach ,  Ulrich Theus

发明人： Reiner Bidenbach ,  Ulrich Theus

IPC分类号： H03K1792

CPC分类号： G06G7/186

摘要： In integrators which integrate the analog photocurrent of a photodiode (PD), the amplification-bandwidth product is relatively small on account of the parallel parasitic capacitance (Cp) of the photodiode (PD). However, in a design with a switched capacitor (C1), the bandwidth and at the same time the DC amplification must be large, so as to assure the integrator function even at low frequencies. So as to fulfill both of these mutually contradictory requirements for large bandwidth and high DC amplification, a reference voltage (V1) is present at a voltage divider that includes a resistor (R2) and a circuit section (R1) connected in series thereto, as well as at the photodiode (PD). The connection point of the voltage divider is connected to the inverting input of the transconductance amplifier (V). In a preferred embodiment, the circuit section (R1) is realized as a switched capacitor (C1), and the resistance (R2) is realized as an MOS transistor (T1). As an integrated switching circuit, the invention is especially suited for sigma-delta-analog converters.

摘要翻译： 在集成了光电二极管（PD）的模拟光电流的积分器中，由于光电二极管（PD）的并联寄生电容（Cp），放大带宽乘积相对较小。 然而，在具有开关电容器（C1）的设计中，带宽并且同时DC放大必须大，以便即使在低频下也能确保积分器的功能。 为了满足这两个相互矛盾的大带宽和高直流放大的要求，在包括电阻器（R2）和串联连接的电路部分（R1）的分压器上存在参考电压（V1），如 以及光电二极管（PD）。 分压器的连接点连接到跨导放大器（V）的反相输入端。 在优选实施例中，电路部分（R1）被实现为开关电容器（C1），并且电阻（R2）被实现为MOS晶体管（T1）。 作为集成开关电路，本发明特别适用于Σ-Δ模拟转换器。

公开(公告)号：US06300806B1

公开(公告)日：2001-10-09

申请号：US09448049

申请日：1999-11-23

申请人： Ulrich Theus ,  Reiner Bidenbach

发明人： Ulrich Theus ,  Reiner Bidenbach

IPC分类号： H03K300

CPC分类号： G06G7/28

摘要： A function generator includes a switching stage for forming a defined signal waveform. The switching stage includes switching transistors that are turned on in a predetermined sequence of undelayed and delayed clock signals, with an output node summing the output currents of the switching transistors. The function generator also includes a delay device that generates the undelayed and delayed clock signals from an applied clock signal. The delays of the delayed clock signals define predetermined instants within at least one period of the applied clock signal. The switching edge is divided into different time ranges whose respective edge steepnesses are adjustable independently of each other. By point-mirroring the signal waveform about a medium value of the signal edge, frequencies at twice, four times, six times, etc. the frequency of the fundamental signal frequency are reduced. Due to the sinusoidal shape of the switching edges, electromagnetic emissions are reduced because of the reduced amplitude of the harmonics. The electromagnetic emission reduction applies both to pure clock signals and to other digital signals, including control, data, or supply lines.

摘要翻译： 函数发生器包括用于形成定义的信号波形的切换级。 开关级包括以预定顺序的未延迟和延迟的时钟信号导通的开关晶体管，输出节点对开关晶体管的输出电流求和。 函数发生器还包括延迟器件，其从施加的时钟信号产生未延迟和延迟的时钟信号。 延迟的时钟信号的延迟在施加的时钟信号的至少一个周期内限定预定时刻。 切换边缘被分成不同的时间范围，其各个边缘陡度彼此独立地可调。 通过对信号边缘的中值的信号波形进行点反射，减少了基频信号频率的两倍，四倍，六倍等频率。 由于开关边缘的正弦形状，由于谐波的幅度减小，电磁辐射减少。 电磁辐射减少既适用于纯时钟信号，又适用于其他数字信号，包括控制，数据或电源线。

公开(公告)号：US5844427A

公开(公告)日：1998-12-01

申请号：US806905

申请日：1997-02-26

申请人： Ulrich Theus ,  Mario Motz

发明人： Ulrich Theus ,  Mario Motz

IPC分类号： G01D3/028 ,  G01D3/02 ,  G01D5/14 ,  G01R33/06

CPC分类号： G01D3/02 ,  G01D5/142

摘要： A monolithic integrated sensor circuit is disclosed comprising a sensor system for generating an electronic sensor signal; a supply unit for the sensor system; an amplifying stage for amplifying the sensor signal; a plurality of inverting devices in the signal path of the amplifying stage which reverse the polarity of the sensor signal at equal time intervals, the time intervals and inversion of the sensor signal being controlled by a clock signal source; and an averaging combiner stage whose input receives an amplified sensor signal and whose output has a reference polarity which is controlled by means of the inverting devices in such a way as to be always the same regardless of the switching state in the signal path. The monolithic integrated sensor circuit of the present invention minimizes the offset error.

摘要翻译： 公开了一种单片集成传感器电路，其包括用于产生电子传感器信号的传感器系统; 用于传感器系统的供应单元; 用于放大传感器信号的放大级; 放大级的信号路径中的多个反相器件以相等的时间间隔反转传感器信号的极性，传感器信号的时间间隔和反相由时钟信号源控制; 以及平均组合器级，其输入接收放大的传感器信号，并且其输出具有通过反相器件控制的参考极性，使得总是相同的方式，而不管信号路径中的开关状态如何。 本发明的单片集成传感器电路使偏移误差最小化。

公开(公告)号：US5751826A

公开(公告)日：1998-05-12

申请号：US654372

申请日：1996-05-28

申请人： Ulrich Theus

发明人： Ulrich Theus

IPC分类号： H03G3/02 ,  H03F3/181 ,  H04H60/04 ,  H04B1/00

CPC分类号： H04H60/04

摘要： A monolithic integrable mixer network for a mixer console includes a variable gain preamplifier for each sound channel, a summing amplifier whose summing gain is adjustable differently for each sound channel, and a control unit which divides the channel gain for the respective sound channel between the preamplifier and the summing amplifier according to a ratio dependent on the desired channel gain to optimize the noise performance of the mixer network.

摘要翻译： 用于混合器控制台的单片可积分混频器网络包括用于每个声道的可变增益前置放大器，一个求和放大器，其求和增益对于每个声道的调节方式不同;以及控制单元，其将前置放大器 以及根据所需信道增益的比例的求和放大器，以优化混频器网络的噪声性能。

公开(公告)号：US5699005A

公开(公告)日：1997-12-16

申请号：US563173

申请日：1995-11-27

申请人： Andreas Menkhoff ,  Ulrich Theus

发明人： Andreas Menkhoff ,  Ulrich Theus

IPC分类号： G06F1/025 ,  G06F1/04 ,  H03C3/00 ,  H03K3/84 ,  H03K5/13 ,  H03K5/133 ,  H03K7/06 ,  H03K1/04

CPC分类号： H03K7/06 ,  G06F1/025 ,  G06F1/04 ,  H03K5/133 ,  H04B2215/064 ,  H04B2215/067

摘要： A clock generator circuit for clock controlled electronic devices, which causes minimal electromagnetic interference in adjacent electronic equipment. The clock generator circuit includes a clock source for generating a basic clock signal having a predetermined frequency. The basic clock signal defines a reference clock signal having a period T. A phase modulator coupled to the clock source for producing a system clock signal by delaying the basic clock signal. A signal source coupled to the phase modulator, which controls the phase modulator so that the system clock signal is delayed with respect to the reference clock signal by a time period less than half of the period T of the reference clock signal.

摘要翻译： 用于时钟控制电子设备的时钟发生器电路，其在相邻电子设备中引起最小的电磁干扰。 时钟发生器电路包括用于产生具有预定频率的基本时钟信号的时钟源。 基本时钟信号定义具有周期T的参考时钟信号。相位调制器，耦合到时钟源，用于通过延迟基本时钟信号产生系统时钟信号。 耦合到相位调制器的信号源，其控制相位调制器，使得系统时钟信号相对于参考时钟信号延迟小于参考时钟信号的周期T的一半的时间周期。

公开(公告)号：US5654629A

公开(公告)日：1997-08-05

申请号：US608146

申请日：1996-02-28

申请人： Ulrich Theus

发明人： Ulrich Theus

IPC分类号： G05F3/26 ,  H03F3/343 ,  G05F3/16

CPC分类号： G05F3/262 ,  H01L2924/0002

摘要： A current mirror circuit including at least one current bank transistor coupled to a cascade transistor. The cascade transistor further coupled to a current mirror input. A current-controlled current source operable for both receiving a differential current from said current mirror input and for producing a charging current for charging a gate of the at least one current bank transistor in order to null the differential current.

摘要翻译： 电流镜电路，包括耦合到级联晶体管的至少一个电流库晶体管。 级联晶体管还耦合到电流镜输入。 电流控制电流源，其可操作以接收来自所述电流镜输入的差分电流，并产生用于对所述至少一个电流库晶体管的栅极充电的充电电流，以使所述差分电流无效。

公开(公告)号：US5446380A

公开(公告)日：1995-08-29

申请号：US164188

申请日：1993-12-09

申请人： Ulrich Theus ,  Juergen Kessel

发明人： Ulrich Theus ,  Juergen Kessel

IPC分类号： G05F1/56 ,  G05F1/563 ,  G05F1/575 ,  H03F1/30 ,  G05F1/565

CPC分类号： G05F1/563 ,  G05F1/575 ,  H03F1/305 ,  Y10S323/901

摘要： A voltage regulator in the form of a series regulator for generating a regulated supply voltage includes a control loop with a reference network, a difference device, and a control element. The control element is connected between a first terminal and a second terminal. The power supply for the reference network and the difference device is coupled to the second terminal. During a starting phase, a starting device with an auxiliary circuit pulls the control loop into the regular operating range.

摘要翻译： 用于产生稳定电源电压的串联调节器形式的电压调节器包括具有参考网络的控制回路，差分装置和控制元件。 控制元件连接在第一端子和第二端子之间。 参考网络和差分装置的电源耦合到第二终端。 在启动阶段，具有辅助电路的起动装置将控制回路拉到常规工作范围。

公开(公告)号：US5182525A

公开(公告)日：1993-01-26

申请号：US805731

申请日：1991-12-09

申请人： Ulrich Theus

发明人： Ulrich Theus

IPC分类号： H03F1/02 ,  H03F1/52 ,  H03F3/45

CPC分类号： H03F3/3066 ,  H03F1/0261 ,  H03F1/523 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2203/45112 ,  H03F2203/45188 ,  H03F2203/45281 ,  H03F2203/45466 ,  H03F2203/45471

摘要： A CMOS transconductance amplifier with a floating operating point which has low quiescent-current consumption for a voltage-to-current converter. On the other hand, the current yield of the output transistor in an output current mirror for a load current is high. The low quiescent-current consumption is achieved by connecting a coupling transistor used as a low-impedance diode in parallel with an active load in the current output stage of the voltage-to-current converter. The high current yield is achieved by means of a positive-feedback circuit which adds to the quiescent current of the voltage-to-current converter an auxiliary current proportional to the load current, thus forming a floating operating point.

摘要翻译： 具有浮动工作点的CMOS跨导放大器，对于电压 - 电流转换器具有低静态电流消耗。 另一方面，用于负载电流的输出电流镜中的输出晶体管的当前产量高。 通过将用作低阻抗二极管的耦合晶体管与电压 - 电流转换器的电流输出级中的有源负载并联，实现低静态电流消耗。 通过正反馈电路实现高电流产量，其将电压 - 电流转换器的静态电流加到与负载电流成比例的辅助电流，从而形成浮动工作点。

公开(公告)号：US5146225A

公开(公告)日：1992-09-08

申请号：US706494

申请日：1991-05-28

申请人： Ulrich Theus

发明人： Ulrich Theus

IPC分类号： H03M1/08 ,  H03M1/86 ,  H03M3/02

CPC分类号： H03M3/504

摘要： A CMOS circuit for averaging digital-to-analog converters includes a shift register of series-connected master and slave cells controlled by a shift clock. The input of the shift register is supplied with a pulse-density-modulated data signal, and the outputs of each of the master and slave cells are connected to a data-dependent control input of a multistage gate circuit. The gate circuits are controlled by a gate clock and cause constant currents to be switched via two buses to the input and output of a p-channel current mirror in accordance with the state of the master or slave cell. The input of a current mirror is constantly supplied with one-half the sum current of the constant-current sources, and the current mirror provides current scaling, preferably by a factor of 0.5.

摘要翻译： 用于平均数模转换器的CMOS电路包括由移位时钟控制的串联主和从单元的移位寄存器。 移位寄存器的输入被提供脉冲密度调制数据信号，并且每个主单元和从单元的输出连接到多级门电路的依赖于数据的控制输入。 栅极电路由栅极时钟控制，并且根据主单元或从单元的状态使恒定电流通过两个总线切换到p沟道电流镜的输入和输出。 电流镜的输入始终被提供恒流源的总和电流的一半，电流镜提供电流缩放，优选为0.5倍。