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公开(公告)号：US11171653B2
公开(公告)日：2021-11-09
申请号：US16957428
申请日：2017-12-28
IPC分类号： H03K19/17704 , H03K19/17736 , H03K19/1776 , H03K19/17764
摘要： A method for programming a Field Programmable Gate Array (FPGA) via a network, the network being operated according to a predetermined communications protocol, can include: establishing a communication connection between the FPGA and an external master, setting the FPGA into a programming mode, the master providing an FPGA programming image to the FPGA in a sequence of frames so that the frames can be parsed and enabling the FPGA to write only during receiving the payload section of the frames. The FPGA programming image and parsing the sequence of frames can be performed by a permanently programmed or hardwired logic component. A network, FPGA, and a communication system can be configured to utilize embodiments of the method.
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公开(公告)号：US11227092B2
公开(公告)日：2022-01-18
申请号：US17186415
申请日：2021-02-26
IPC分类号： G06F30/392 , G06F115/12 , H05K13/00
摘要： A main board for a computer device can include main board components arranged on a first surface of the main board and Trusted Platform Module (TPM) components arranged on the first surface of the main board. The TPM components can be located in a predetermined area of the main board that is detachable from the main board (e.g. by means of a predetermined break line). A method for producing an embodiment of the main board with an integrated TPM can include producing a Printed Circuit Board (PCB); arranging a plurality of main board components in a first area of the PCB; and arranging TPM components in a second area of the PCB that is a detachable predetermined area of the main board. A predetermined breakline which at least partly surrounds the predetermined area can be formed by drilling holes to form a perforated line.
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3.发明申请公开(公告)号：US20190342116A1
公开(公告)日：2019-11-07
申请号：US16476670
申请日：2017-01-11
IPC分类号： H04L12/42
摘要： When operating a first unit in a daisy chain of units allowing bidirectional communication, each unit is capable to transmit and to receive signals. A plurality of units including the said first unit transmits a respective signal to a preceding neighbor unit preceding in said daisy chain and to a following neighbor unit following in the daisy chain. In the daisy chain, the first unit determines whether or not it receives a signal from both of these neighbor units or not and if so, said first unit operates so as to put the at least one subunit into a first state. If the at least one subunit is not put into a first state, it operates so as to put the at least one subunit into a second state different from said first state.
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公开(公告)号：US20210271798A1
公开(公告)日：2021-09-02
申请号：US17186415
申请日：2021-02-26
IPC分类号： G06F30/392
摘要： A main board for a computer device can include main board components arranged on a first surface of the main board and Trusted Platform Module (TPM) components arranged on the first surface of the main board. The TPM components can be located in a predetermined area of the main board that is detachable from the main board (e.g. by means of a predetermined break line). A method for producing an embodiment of the main board with an integrated TPM can include producing a Printed Circuit Board (PCB); arranging a plurality of main board components in a first area of the PCB; and arranging TPM components in a second area of the PCB that is a detachable predetermined area of the main board. A predetermined breakline which at least partly surronds the predetermined area can be formed by drilling holes to form a perforated line.
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公开(公告)号：US10958473B2
公开(公告)日：2021-03-23
申请号：US16476670
申请日：2017-01-11
摘要： When operating a first unit in a daisy chain of units allowing bidirectional communication, each unit is capable to transmit and to receive signals. A plurality of units including the said first unit transmits a respective signal to a preceding neighbor unit preceding in said daisy chain and to a following neighbor unit following in the daisy chain. In the daisy chain, the first unit determines whether or not it receives a signal from both of these neighbor units or not and if so, said first unit operates so as to put the at least one subunit into a first state. If the at least one subunit is not put into a first state, it operates so as to put the at least one subunit into a second state different from said first state.
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公开(公告)号：US11804666B2
公开(公告)日：2023-10-31
申请号：US17280234
申请日：2018-09-28
发明人： Marcelo Samsoniuk , Osvaldo Sato , Diogo Granado
IPC分类号： H01R13/60 , H01R12/70 , H01R12/72 , H01R13/514 , H05K1/18
CPC分类号： H01R12/7052 , H01R12/7064 , H01R12/7076 , H01R12/727 , H01R13/514 , H05K1/181 , H05K2203/1572
摘要： An electrical connector mountable to a substrate (e.g. a Printed Circuit Board, PCB) can include a terminal housing having a front wall and an opposing back wall. An opening is provided in the front wall for receiving a plug inside the terminal housing, opposing side walls, and a top wall and an opposing bottom wall. The bottom wall has an inner surface facing the inside of the terminal housing and an outer surface facing away from the inside of the terminal housing. The outer surface (can have at least two retention pins projecting from the outer surface for being inserted into corresponding holes in the PCB. A first retention pin can be positioned on the outer surface so as to be arranged asymmetrically with respect to a second retention pin.
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公开(公告)号：US20200321965A1
公开(公告)日：2020-10-08
申请号：US16957428
申请日：2017-12-28
IPC分类号： H03K19/17764 , H03K19/1776 , H03K19/17736 , H03K19/17704
摘要： A method for programming a Field Programmable Gate Array (FPGA) via a network, the network being operated according to a predetermined communications protocol, can include: establishing a communication connection between the FPGA and an external master, setting the FPGA into a programming mode, the master providing an FPGA programming image to the FPGA in a sequence of frames so that the frames can be parsed and enabling the FPGA to write only during receiving the payload section of the frames. The FPGA programming image and parsing the sequence of frames can be performed by a permanently programmed or hardwired logic component. A network, FPGA, and a communication system can be configured to utilize embodiments of the method.
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