公开(公告)号：US20240224428A1

公开(公告)日：2024-07-04

申请号：US18092912

申请日：2023-01-03

申请人： Simetric Semiconductor Solutions Co., Ltd.

发明人： Marcus Elmar Lang ,  Kei Ming Yip

IPC分类号： H05K3/00

CPC分类号： H05K3/0085 ,  H05K2203/1518 ,  H05K2203/1545 ,  H05K2203/1572

摘要： The present invention discloses a three-dimensional circuit board processing apparatus, including an input module, a vertical processing module, and an output module, which are arranged in sequence. The vertical processing module includes a conveying unit and a processing assembly. A vertical conveying port is arranged on each of two sides of the vertical processing module. The input module is connected to one end of the conveying unit, and the output module is connected to another end of the conveying unit. The input module and/or the output module are/is a flippable module. According to embodiments of the present invention, by arranging the flippable input module and/or output module, the circuit board may enter and exit the vertical processing module vertically, and may be uniformly processed through the vertical processing module, thereby enhancing the processing quality of the circuit board and improving the automation performance of three-dimensional processing.

公开(公告)号：US11963306B2

公开(公告)日：2024-04-16

申请号：US16633840

申请日：2018-06-29

申请人： Gebr. Schmid GmbH

发明人： Christian Schmid

IPC分类号： H05K3/06 ,  H01L21/67

CPC分类号： H05K3/068 ,  H01L21/6708 ,  H05K3/064 ,  H05K2203/0165 ,  H05K2203/0169 ,  H05K2203/075 ,  H05K2203/1509 ,  H05K2203/1554 ,  H05K2203/1572

摘要： A method of manufacturing printed circuit boards includes some or all of: chemically or electrically applying metallic layers to a substrate; incorporating bores into the substrate; through-contacting the bores incorporated into the substrate; applying a layer from a photoresist to an electrically conducting layer in a masking step; exposing the photoresist while using an exposure mask in an exposing step; removing exposed or unexposed regions of the layer from the photoresist while in regions laying bare the electrically conducting layer in a developing step; removing the laid-bare regions of the electrically conducting layer in an etching step; cleaning the substrate in a rinsing step; and drying the substrate, wherein the substrate for carrying out the developing step and/or the etching step is set in rotation and a developer solution and/or an etching liquid is applied to the rotating substrate by at least one nozzle.

公开(公告)号：US20230380075A1

公开(公告)日：2023-11-23

申请号：US18229717

申请日：2023-08-03

申请人： Murata Manufacturing Co., Ltd.

发明人： Kenji MATSUDA

IPC分类号： H05K3/46 ,  H05K3/30 ,  H05K1/02 ,  H05K1/18

CPC分类号： H05K3/4644 ,  H05K3/303 ,  H05K1/0242 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/09354 ,  H05K2203/1572 ,  H05K2201/10098

摘要： A multilayer body includes insulator layers including a first insulator layer laminated in a vertical direction. Electrodes include a signal electrode and are provided at an upper main surface of the first insulator layer and arranged in a transverse direction. At least a portion of each of the electrodes is exposed to outside from a circuit board. First and second interlayer connection conductors extend through the first insulator layer in the vertical direction and electrically connect the signal electrode and a signal conductor layer. Mounting portions are located at the portions of the electrodes that are exposed to the outside from the circuit board. The first and second interlayer connection conductors are electrically connected to the signal electrode so as not to overlap the mounting portion that is provided at the signal electrode.

公开(公告)号：US20230262904A1

公开(公告)日：2023-08-17

申请号：US18012103

申请日：2021-07-01

申请人： Peters Research GmbH & Co. Kommanditgesellschaft

发明人： Ralf SCHWARTZ ,  Michael MÜLLER ,  Johannes TEKATH

IPC分类号： H05K3/00

CPC分类号： H05K3/0094 ,  H05K2203/013 ,  H05K2203/0763 ,  H05K2203/1572 ,  H05K2201/0959

摘要： A method for closing a channel-shaped opening with a cross-sectional area and a passage length, more particularly through-bores or plated through-holes in printed circuit boards, using a liquid curable or curing filler material. The opening is closed by a digitally controlled application method with two discharge heads arranged opposite one another, preferably in an inkjet method with two discharge heads designed as print heads and arranged opposite one another. The two discharge heads are controlled such that the opening is filled with the filler material from both sides through the two ends simultaneously. The filler material is discharged by the two discharge heads such that the quantities of discharged filler material meet inside the opening.

公开(公告)号：US20190124767A1

公开(公告)日：2019-04-25

申请号：US16169340

申请日：2018-10-24

申请人： IBIDEN CO., LTD.

发明人： Takema ADACHI ,  Toshihide MAKINO ,  Hidetoshi NOGUCHI

IPC分类号： H05K1/11 ,  H05K3/46 ,  H05K1/03 ,  H05K3/06 ,  H05K3/42

CPC分类号： H05K1/115 ,  H05K1/0373 ,  H05K3/06 ,  H05K3/422 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/09227 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09727 ,  H05K2201/09827 ,  H05K2201/099 ,  H05K2203/072 ,  H05K2203/107 ,  H05K2203/1572

摘要： A printed wiring board includes: a core substrate having a core layer, first and second conductor layers, and through-hole conductors penetrating through the core layer and connecting the conductor layers; and first and second build-up layers each including an insulating layer, an inner side conductor layer, an outermost insulating layer, an outermost conductor layer, and a solder resist layer. Each of the conductor layers includes conductor circuits having substantially a trapezoid cross-sectional shape, and spaces between adjacent conductor circuits, and includes a metal foil, a seed layer, and an electrolytic plating film. The inner side conductor layers have the smallest minimum circuit width, the smallest minimum space width and the largest base angle among the conductor layers. The insulating layers have the smallest ten-point average roughness rz3, rz7 among the ten-point average roughness rz3, rz7, rz1, rz2, rz5 and rz9 of the core layer, insulating layers and outermost insulating layers.

公开(公告)号：US20180231932A1

公开(公告)日：2018-08-16

申请号：US15887060

申请日：2018-02-02

申请人： CANON KABUSHIKI KAISHA

发明人： Taro Minobe ,  Norikazu Sugiyama ,  Ryo Matsumura

IPC分类号： H05K7/00 ,  H01L41/04 ,  H05K3/30 ,  H01L41/107 ,  H05K1/18 ,  H02M3/335

CPC分类号： G03G15/80 ,  H01L41/044 ,  H01L41/053 ,  H01L41/107 ,  H02M3/33507 ,  H05K1/181 ,  H05K3/303 ,  H05K3/3415 ,  H05K3/3494 ,  H05K2201/10083 ,  H05K2201/10545 ,  H05K2203/1572

摘要： A printed circuit board comprises a first mounting surface, a second mounting surface, and a piezoelectric transformer. The piezoelectric transformer has a piezoelectric substance, external electrodes, and a frame substrate. The second mounting surface has a projection region. There is a first region from a first location, where an end portion further from the output electrode out of end portions of the input electrode is projected onto the second mounting surface in the projection region, to a second location, where an end portion closer to the output electrode out of the end portions of the input electrode is projected onto the second mounting surface, the first region being a mounting allowed region where an electronic component is mounted.

公开(公告)号：US20180054900A1

公开(公告)日：2018-02-22

申请号：US15557255

申请日：2016-03-10

申请人： SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

发明人： Hiroshi UEDA ,  Kousuke MIURA ,  Yoshihito YAMAGUCHI ,  Yuka URABE

IPC分类号： H05K3/46 ,  H01F41/04 ,  H01F41/12 ,  H01F27/32

CPC分类号： H05K3/4673 ,  H01F17/0013 ,  H01F27/327 ,  H01F41/041 ,  H01F41/043 ,  H01F41/127 ,  H01F2017/0073 ,  H05K1/165 ,  H05K3/241 ,  H05K3/4626 ,  H05K3/4644 ,  H05K2203/1476 ,  H05K2203/1572

摘要： A planar coil element of the present invention includes an insulating base film having a first surface and a second surface opposite to the first surface, a first conductive pattern deposited on the first surface side of the insulating base film, and a first insulating layer covering the first conductive pattern on the first surface side, in which the first conductive pattern includes a core body and a widening layer deposited by plating on the outer surface of the core body, and the ratio of the average thickness of the first conductive pattern to the average circuit pitch of the first conductive pattern is ½ or more and 5 or less.

公开(公告)号：US20180009046A1

公开(公告)日：2018-01-11

申请号：US15543836

申请日：2015-11-26

申请人： SHODA TECHTRON CORP.

发明人： Tetsuya SHIMAMURA ,  Kazuhiro NAKIRI

IPC分类号： B23D45/10 ,  B23D59/00 ,  B28D1/04 ,  H05K3/00

CPC分类号： B23D45/105 ,  B23D47/12 ,  B23D59/001 ,  B28D1/048 ,  H05K3/0052 ,  H05K2203/0228 ,  H05K2203/1572

摘要： A substrate cutting device includes: a first cutter including a plurality of first rotary blades; a second cutter including a plurality of second rotary blades; a first rotation drive unit for rotationally driving the first cutter; a second rotation drive unit for rotationally driving the second cutter; a cutter support unit; and a phase adjustment unit. The cutter support unit supports the first cutter and the second cutter such that the first and second cutters are radially opposed to each other so that rotation axes thereof are parallel to each other. The phase adjustment unit adjusts a phase of at least one of the first cutter and the second cutter such that each of the second rotary blades is located between two adjacent first rotary blades in an opposing area in which the first cutter and the second cutter are opposed to each other.

公开(公告)号：US20170354043A1

公开(公告)日：2017-12-07

申请号：US15172652

申请日：2016-06-03

申请人： International Business Machines Corporation

发明人： Eric J. Campbell ,  Joseph Kuczynski ,  Timothy J. Tofil

IPC分类号： H05K3/46 ,  H05K1/02 ,  H05K1/11

CPC分类号： H05K3/4611 ,  H05K1/0212 ,  H05K1/167 ,  H05K3/4092 ,  H05K3/4602 ,  H05K2201/09263 ,  H05K2203/065 ,  H05K2203/068 ,  H05K2203/1115 ,  H05K2203/1572

摘要： A multi-layer printed circuit board (PCB) includes a laminate between a PCB heating core and a PCB signal core. The PCB heating core includes an electrically conductive resistive heating element upon a first core substrate. During a lamination cure PCB fabrication stage, a platen contacts the PCB and a power supply is electrically connected to the resistive heating element. The laminate is cured with heat transferred by the platen and heat from the resistive heating element. The PCB heating core may be located within an inner layer of the multi-layer PCB to normalize a thermal gradient across the multi-layer PCB that may otherwise occur during the laminate cure fabrication stage. As a result of the normalized thermal gradient, the degree of laminate cure and material characteristics of the cured laminate material are more consistent throughout the multi-layer PCB thickness.

公开(公告)号：US09769932B2

公开(公告)日：2017-09-19

申请号：US15148780

申请日：2016-05-06

申请人： MUTRACX INTERNATIONAL B.V.

发明人： Henk Jan Zwiers ,  Jacobus Hendricus Johannes Janssen ,  Joost Anne Veerman

IPC分类号： H05K3/12 ,  B05B13/02 ,  B05B15/04 ,  H01L21/288 ,  H01L23/544 ,  G01N21/956 ,  H05K3/00 ,  H05K3/22 ,  B05B1/08 ,  H01L21/66 ,  H05K1/09 ,  H05K3/06

CPC分类号： H05K3/125 ,  B05B1/08 ,  B05B12/16 ,  B05B13/0221 ,  B41J2/16538 ,  B41J2/16544 ,  B41J2/2132 ,  B41J25/001 ,  G01N21/95607 ,  G01N2021/95615 ,  H01L21/288 ,  H01L22/12 ,  H01L23/544 ,  H01L2924/0002 ,  H05K1/092 ,  H05K3/0079 ,  H05K3/061 ,  H05K3/22 ,  H05K2203/013 ,  H05K2203/1461 ,  H05K2203/1563 ,  H05K2203/1572 ,  H05K2203/16 ,  H05K2203/162 ,  H05K2203/163 ,  H01L2924/00

摘要： A printing process for printing an ink pattern on a substrate is provided. The ink pattern to be printed is based on an available pattern layout. The pattern layout defines a desired layout of the ink pattern to be printed. Based on the pattern layout an input image for allocating dot positions of the ink pattern is generated. The printing process includes a step of comparing a scan image with the input image to carry out a quality inspection to detect any print defects in the printed ink pattern. The printing process includes a step of providing a decision on an approval or a rejection of the printed ink pattern. In case of an approval, the substrate can be supplied to a subsequent processing station to finalize the substrate. In case of a rejection, the substrate including print defects can be recycled.