公开(公告)号：US11778830B2

公开(公告)日：2023-10-03

申请号：US17979789

申请日：2022-11-03

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang

IPC: H10B43/30 ,  H10B41/10 ,  H10B41/30 ,  H10B43/10

CPC classification number: H10B43/30 ,  H10B41/10 ,  H10B41/30 ,  H10B43/10

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

公开(公告)号：US20210028025A1

公开(公告)日：2021-01-28

申请号：US17067409

申请日：2020-10-09

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang ,  Chin-Chin Tsai

IPC: H01L21/321 ,  H01L21/3213 ,  H01L29/423 ,  H01L27/11568

Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.

公开(公告)号：US11581325B2

公开(公告)日：2023-02-14

申请号：US17201986

申请日：2021-03-15

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang

IPC: H01L27/11568 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11519

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

公开(公告)号：US20220223612A1

公开(公告)日：2022-07-14

申请号：US17201986

申请日：2021-03-15

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang

IPC: H01L27/11568 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

公开(公告)号：US20230046058A1

公开(公告)日：2023-02-16

申请号：US17979789

申请日：2022-11-03

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang

IPC: H01L27/11568 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

公开(公告)号：US11348805B2

公开(公告)日：2022-05-31

申请号：US17067409

申请日：2020-10-09

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang ,  Chin-Chin Tsai

IPC: H01L29/423 ,  H01L21/321 ,  H01L21/3213 ,  H01L27/11568

Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.