公开(公告)号：US11348805B2

公开(公告)日：2022-05-31

申请号：US17067409

申请日：2020-10-09

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang ,  Chin-Chin Tsai

IPC: H01L29/423 ,  H01L21/321 ,  H01L21/3213 ,  H01L27/11568

Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.

公开(公告)号：US11777007B2

公开(公告)日：2023-10-03

申请号：US17204642

申请日：2021-03-17

Applicant: United Microelectronics Corp.

Inventor： Chin-Chin Tsai

IPC: H01L29/792 ,  H01L29/423 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/42344 ,  H01L21/02238 ,  H01L21/76224 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for fabricating memory device is provided. The method comprises forming a cell structure on a substrate, wherein the cell structure comprises a first gate structure and a second gate structure disposed on a substrate and an insulating layer in contact between the first gate structure and the second gate structure, wherein the first gate structure and the second gate structure are planarized and the first gate structure is for storing charges. Further, the first gate structure and the second gate structure are patterned to have a shallow indent above the insulating layer. An isolation structure is formed in the shallow indent to have a shallow indent isolation.

公开(公告)号：US10991806B2

公开(公告)日：2021-04-27

申请号：US16408214

申请日：2019-05-09

Applicant: United Microelectronics Corp.

Inventor： Chin-Chin Tsai

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: A structure of memory device is provided. The structure of memory device includes a first gate structure, disposed on a substrate, wherein the first gate structure is for storing charges. In addition, a second gate structure is disposed on the substrate. An insulating layer is in contact between the first gate structure and the second gate structure. An isolation structure integrated with the insulating layer is between the first gate structure and the second gate structure and at a top portion of the first gate structure and the second gate structure. The isolation structure provides an isolation distance between the first gate structure and the second gate structure.

公开(公告)号：US10916555B2

公开(公告)日：2021-02-09

申请号：US16264326

申请日：2019-01-31

Applicant: United Microelectronics Corp.

Inventor： Chin-Chin Tsai

IPC: H01L27/11568 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28

Abstract: A structure of memory cell includes a memory gate structure, disposed on a substrate, wherein the substrate has an indent region aside the memory gate structure. A selection gate structure is disposed on the substrate at the indent region aside the memory gate structure. A first insulation layer is at least disposed between the memory gate structure and selection gate structure.

公开(公告)号：US20210028025A1

公开(公告)日：2021-01-28

申请号：US17067409

申请日：2020-10-09

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang ,  Chin-Chin Tsai

IPC: H01L21/321 ,  H01L21/3213 ,  H01L29/423 ,  H01L27/11568

Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.

公开(公告)号：US20210202707A1

公开(公告)日：2021-07-01

申请号：US17204642

申请日：2021-03-17

Applicant: United Microelectronics Corp.

Inventor： Chin-Chin Tsai

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: A method for fabricating memory device is provided. The method comprises forming a cell structure on a substrate, wherein the cell structure comprises a first gate structure and a second gate structure disposed on a substrate and an insulating layer in contact between the first gate structure and the second gate structure, wherein the first gate structure and the second gate structure are planarized and the first gate structure is for storing charges. Further, the first gate structure and the second gate structure are patterned to have a shallow indent above the insulating layer. An isolation structure is formed in the shallow indent to have a shallow indent isolation.

公开(公告)号：US20200251482A1

公开(公告)日：2020-08-06

申请号：US16264326

申请日：2019-01-31

Applicant: United Microelectronics Corp.

Inventor： Chin-Chin Tsai

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28

Abstract: A structure of memory cell includes a memory gate structure, disposed on a substrate, wherein the substrate has an indent region aside the memory gate structure. A selection gate structure is disposed on the substrate at the indent region aside the memory gate structure. A first insulation layer is at least disposed between the memory gate structure and selection gate structure.