公开(公告)号：US10651183B1

公开(公告)日：2020-05-12

申请号：US16221382

申请日：2018-12-14

Applicant: United Microelectronics Corp.

Inventor： Jianjun Yang ,  Cheng-Hua Yang ,  Fan-Chi Meng ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L21/336 ,  H01L27/11517

Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.

公开(公告)号：US09397084B1

公开(公告)日：2016-07-19

申请号：US14636122

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Fan-Chi Meng ,  Shan-Shi Huang

IPC: H01L27/02 ,  H01L21/822 ,  H01L23/528 ,  H01L23/50 ,  H01L29/66 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L27/0255 ,  H01L24/11 ,  H01L24/13 ,  H01L24/43 ,  H01L24/45 ,  H01L27/0296 ,  H01L29/66136 ,  H01L29/861 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A structure of ESD protection circuits on a BEOL layer includes a substrate. A plurality of interconnect layers and an inter-level dielectric layer are disposed on the substrate. The inter-level dielectric layer is disposed between the plurality of interconnect layers. The last layer of the interconnect layers comprises an I/O pad, a first pad and a second pad. A first diode and a second diode are disposed on the last layer of the inter-level dielectric layer, wherein the first diode electrically connects to the I/O pad and the first pad and the second diode electrically connects to the I/O pad and the second pad.

Abstract translation: BEOL层上的ESD保护电路的结构包括基板。 多个互连层和层间电介质层设置在基板上。 层间电介质层设置在多个互连层之间。 互连层的最后一层包括I / O焊盘，第一焊盘和第二焊盘。 第一二极管和第二二极管设置在层间电介质层的最后一层上，其中第一二极管电连接到I / O焊盘，第一焊盘和第二二极管电连接到I / O焊盘， 第二垫。