公开(公告)号：US10008573B1

公开(公告)日：2018-06-26

申请号：US15450030

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Hsuan-Kai Chen ,  Tun-Jen Cheng

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/404 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/7833 ,  H01L29/7835

Abstract: A high-voltage metal-oxide-semiconductor transistor device includes a semiconductor substrate, a gate structure, a first drift region, a first isolation structure, a drain region, and a first sub-gate structure. The gate structure and the first sub-gate structure are disposed on the semiconductor substrate and separated from each other. The first drift region is disposed in the semiconductor substrate and disposed at one side of the gate structure. The first isolation structure and the drain region are disposed in the first drift region and separated from each other. A part of the first drift region is disposed between the drain region and the first isolation structure. The first sub-gate structure is at least partially disposed on the first drift region disposed between the drain region and the first isolation structure, and the first sub-gate structure is electrically connected to the drain region.

公开(公告)号：US20250048671A1

公开(公告)日：2025-02-06

申请号：US18459454

申请日：2023-09-01

Applicant: United Microelectronics Corp.

Inventor： Hsuan-Kai Chen ,  Tun-Jen Cheng ,  Ching-Chung Yang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423

Abstract: A transistor structure including a substrate, a gate dielectric layer, a gate, a first doped region, a second doped region, a first drift region, and a dummy gate is provided. The gate dielectric layer is located on the substrate. The gate dielectric layer includes first and second portions. The second portion is connected to the first portion. The thickness of the second portion is greater than the thickness of the first portion. The gate is located on the first and second portions. The first doped region and the second doped region are located in the substrate on two sides of the gate dielectric layer. The first drift region is located in the substrate on one side of the gate. The second doped region is located in the first drift region. The dummy gate is located on the second portion between the gate and the second doped region.