公开(公告)号：US10431655B2

公开(公告)日：2019-10-01

申请号：US15924001

申请日：2018-03-16

申请人： United Microelectronics Corp.

发明人： Yen-Ming Chen ,  Chiu-Ling Lee ,  Min-Hsuan Tsai ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC分类号： H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

摘要： A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

公开(公告)号：US09224857B2

公开(公告)日：2015-12-29

申请号：US13674146

申请日：2012-11-12

申请人： UNITED MICROELECTRONICS CORP.

发明人： Wei-Lin Chen ,  Chih-Chien Chang ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Chiu-Ling Lee

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/66681

摘要： A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

摘要翻译： 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插塞穿透隔离并到达其底部; 以及具有第二导电类型的第一掺杂电极区域，形成在第二阱内并在隔离件下方以连接导电插塞。

公开(公告)号：US20150014768A1

公开(公告)日：2015-01-15

申请号：US13938252

申请日：2013-07-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Wei-Lin Chen ,  Tseng-Hsun Liu ,  Kuan-Yu Chen ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66704 ,  H01L29/7825

摘要： A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

摘要翻译： 横向双扩散金属氧化物半导体晶体管器件包括其中形成有至少浅沟槽隔离的衬底，包围衬底中的STI的外延层，栅极和漏极区以及形成在衬底中的源极区 在门的相应两侧。 外延层，源极区和漏极区包括第一导电型。 栅极包括形成在基板上的第一部分和延伸到STI中的第二部分。

公开(公告)号：US20140367789A1

公开(公告)日：2014-12-18

申请号：US13918994

申请日：2013-06-17

申请人： UNITED MICROELECTRONICS CORP.

发明人： Wei-Lin Chen ,  Ke-Feng Lin ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Hsuan-Po Liao

IPC分类号： H01L27/088 ,  H01L27/092

CPC分类号： H01L29/7816 ,  H01L27/0207 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/78

摘要： A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

摘要翻译： 提供具有交错布置的用于改善设备的导通电阻和安全操作区域的功率阵列。 每个功率阵列包括两行或更多行，具有沿行排列的多个并行设备单元。 每个器件单元包括源极区域，漏极区域和设置在源极区域和漏极区域之间的栅极，其中每个漏极区域在相邻行的相邻漏极区域沿行方向偏移。

公开(公告)号：US20130256765A1

公开(公告)日：2013-10-03

申请号：US13892324

申请日：2013-05-13

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chu-Chun Chang ,  Chun-Mao Chiou ,  Chiu-Te Lee

IPC分类号： H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7843

摘要： A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property.

摘要翻译： 公开了一种半导体器件。 半导体器件包括：衬底; 设置在所述基板上的栅极结构; 设置在所述栅极结构的侧壁上的第一间隔物; 设置在所述第一间隔件周围的第二间隔件，其中所述第二间隔件包括在所述L形盖层上的L形盖层和盖层; 设置在所述基板中的与所述第二间隔物的两侧相邻的源极/漏极; 以及设置在所述基板上以覆盖所述栅极结构的CESL，其中所述第二间隔物和所述CESL的至少一部分包含相同的化学组成和/或物理性质。

公开(公告)号：US20200266267A1

公开(公告)日：2020-08-20

申请号：US16358556

申请日：2019-03-19

申请人： United Microelectronics Corp.

发明人： HSIANG-HUA HSU ,  Liang-An Huang ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Kuang-Hsiu Chen ,  Ke-Feng Lin ,  Yan-Huei Li ,  Kai-Ting Hu

IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L21/265

摘要： A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

公开(公告)号：US20190245041A1

公开(公告)日：2019-08-08

申请号：US15924001

申请日：2018-03-16

申请人： United Microelectronics Corp.

发明人： Yen-Ming Chen ,  Chiu-Ling Lee ,  Min-Hsuan Tsai ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC分类号： H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/1079 ,  H01L29/0649 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835

摘要： A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

公开(公告)号：US20170162721A1

公开(公告)日：2017-06-08

申请号：US14989814

申请日：2016-01-07

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ke-Feng Lin ,  Hsuan-Po Liao ,  Ming-Shun Hsu ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shih-Teng Huang

IPC分类号： H01L29/861 ,  H01L29/06

CPC分类号： H01L29/8615 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/8613

摘要： A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region.

公开(公告)号：US08941175B2

公开(公告)日：2015-01-27

申请号：US13918994

申请日：2013-06-17

申请人： United Microelectronics Corp.

发明人： Wei-Lin Chen ,  Ke-Feng Lin ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Hsuan-Po Liao

IPC分类号： H01L29/06 ,  H01L29/772 ,  H01L27/088 ,  H01L27/092

CPC分类号： H01L29/7816 ,  H01L27/0207 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/78

摘要： A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

摘要翻译： 提供具有交错布置的用于改善设备的导通电阻和安全操作区域的功率阵列。 每个功率阵列包括两行或更多行，具有沿行排列的多个并行设备单元。 每个器件单元包括源极区域，漏极区域和设置在源极区域和漏极区域之间的栅极，其中每个漏极区域在相邻行的相邻漏极区域沿行方向偏移。

公开(公告)号：US20210134679A1

公开(公告)日：2021-05-06

申请号：US16667921

申请日：2019-10-30

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yuan-Cheng Yang ,  Yi-Han Su ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chun-Lin Chen ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC分类号： H01L21/8234 ,  H01L21/8249

摘要： A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area.