公开(公告)号：US10147800B2

公开(公告)日：2018-12-04

申请号：US15047644

申请日：2016-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Liang Liu ,  Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78

Abstract: A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.

公开(公告)号：US20180114842A1

公开(公告)日：2018-04-26

申请号：US15352558

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Ping-Hung Chiang

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7834

Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

公开(公告)号：US20180097104A1

公开(公告)日：2018-04-05

申请号：US15820467

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US09755046B2

公开(公告)日：2017-09-05

申请号：US15406355

申请日：2017-01-13

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L21/02 ,  H01L29/76 ,  H01L31/062 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/311

CPC classification number: H01L29/66492 ,  H01L21/2652 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of forming a semiconductor device is provided. At least two shallow trenches are formed in a substrate. An insulating layer is formed on surfaces of the substrate and the shallow trenches. A conductive layer is formed on the substrate between the shallow trenches. At least one spacer is formed on a sidewall of the conductive layer, wherein the spacer fills up each shallow trench.

公开(公告)号：US20170110589A1

公开(公告)日：2017-04-20

申请号：US14882663

申请日：2015-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chung Yang ,  Shih-Yin Hsiao

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/4238 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/78

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a diffusion region, a first oxide layer, a second oxide layer and a polysilicon layer. The diffusion region is formed in the substrate and has a source and a drain extended along a first direction. The first oxide layer is formed on the substrate. The second oxide layer is formed in the substrate and adjacent to the drain. The polysilicon layer is formed on the substrate and has a first region, a second region, and a third region. The second region is formed on an edge of the second oxide layer and between the first region and the third region. A width of the second region is less than a width of the first region and a width of the third region along the first direction.

公开(公告)号：US20160343855A1

公开(公告)日：2016-11-24

申请号：US14737186

申请日：2015-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66492 ,  H01L21/2652 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

Abstract: Provided is a semiconductor device including a substrate, an insulating layer, a conductive layer and at least one spacer. The substrate has at least two shallow trenches therein. The conductive layer is disposed on the substrate between the shallow trenches. The insulating layer is disposed between the substrate and the conductive layer. The at least one spacer is disposed on one sidewall of the conductive layer and fills up each shallow trench. A method of forming a semiconductor device is further provided.

Abstract translation: 提供了一种半导体器件，其包括衬底，绝缘层，导电层和至少一个间隔物。 衬底中具有至少两个浅沟槽。 导电层设置在浅沟槽之间的衬底上。 绝缘层设置在基板和导电层之间。 至少一个间隔件设置在导电层的一个侧壁上并填充每个浅沟槽。 还提供了形成半导体器件的方法。

公开(公告)号：US20240234572A1

公开(公告)日：2024-07-11

申请号：US18108019

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang-An Huang ,  Ming-Hua Tsai ,  Wen-Fang Lee ,  Chin-Chia Kuo ,  Jung Han ,  Chun-Lin Chen ,  Ching-Chung Yang ,  Nien-Chung Li

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/7801

Abstract: An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.

公开(公告)号：US11495681B2

公开(公告)日：2022-11-08

申请号：US17067775

申请日：2020-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Shin-Hung Li ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

公开(公告)号：US20220085210A1

公开(公告)日：2022-03-17

申请号：US17067775

申请日：2020-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Shin-Hung Li ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

公开(公告)号：US20220059697A1

公开(公告)日：2022-02-24

申请号：US17065396

申请日：2020-10-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Chung Yang

IPC: H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes: forming a first transistor including: forming a plurality of lightly doped regions in a substrate; forming a first gate structure on the substrate, the first gate structure covering portions of the plurality of lightly doped regions and a portion of the substrate; forming first spacers on sidewalls of the first gate structure; forming doped region in the lightly doped regions; forming an etching stop layer on the substrate; patterning the etching stop layer and the first gate structure to form a second gate structure, and to form a plurality of trenches between the second gate structure and the first spacers; and forming a first dielectric layer on the substrate to cover the etching stop layer and fill the plurality of trenches. The first dielectric layer filled in the trenches is used as virtual spacers.