公开(公告)号：US20250017117A1

公开(公告)日：2025-01-09

申请号：US18236923

申请日：2023-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hsiang Chen ,  Yi-Ching Wang ,  Wei Chen ,  Chia-Fu Cheng ,  Chun-Yao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/20 ,  H10N50/85

Abstract: A magnetic memory device includes a magnetic tunneling junction (MTJ) stack and a capping layer on the MTJ stack. The MTJ stack includes a reference layer, a tunneling barrier layer on the reference layer, and a free layer on the tunneling barrier layer. The capping layer includes a metal under layer that is in direct contact with the free layer, an oxide capping layer on the metal under layer, and a metal protection layer on the oxide capping layer.

公开(公告)号：US20200168450A1

公开(公告)日：2020-05-28

申请号：US16203212

申请日：2018-11-28

Applicant: United Microelectronics Corp.

Inventor： Ko-Wei Lin ,  Kuan-Hsiang Chen ,  Hsin-Fu Huang ,  Chun-Ling Lin ,  Sheng-Yi Su ,  Pei-Hsun Kao

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768

Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.