公开(公告)号：US20250017117A1

公开(公告)日：2025-01-09

申请号：US18236923

申请日：2023-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hsiang Chen ,  Yi-Ching Wang ,  Wei Chen ,  Chia-Fu Cheng ,  Chun-Yao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/20 ,  H10N50/85

Abstract: A magnetic memory device includes a magnetic tunneling junction (MTJ) stack and a capping layer on the MTJ stack. The MTJ stack includes a reference layer, a tunneling barrier layer on the reference layer, and a free layer on the tunneling barrier layer. The capping layer includes a metal under layer that is in direct contact with the free layer, an oxide capping layer on the metal under layer, and a metal protection layer on the oxide capping layer.

公开(公告)号：US11545521B2

公开(公告)日：2023-01-03

申请号：US17157952

申请日：2021-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

公开(公告)号：US10340350B2

公开(公告)日：2019-07-02

申请号：US16044581

申请日：2018-07-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Yun-Tzu Chang ,  Wei-Ning Chen ,  Wei-Ming Hsiao ,  Chia-Chang Hsu ,  Kuo-Chih Lai ,  Yang-Ju Lu ,  Yen-Chen Chen ,  Chun-Yao Yang

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/8234

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

公开(公告)号：US09722030B1

公开(公告)日：2017-08-01

申请号：US15175045

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/165 ,  H01L29/167 ,  H01L23/528 ,  H01L23/532 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US20220320420A1

公开(公告)日：2022-10-06

申请号：US17844741

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yi-Syun Chou ,  Ko-Wei Lin ,  Pei-Hsun Kao ,  Wei Chen ,  Chia-Fu Cheng ,  Chun-Yao Yang ,  Chia-Chang Hsu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

公开(公告)号：US20210143212A1

公开(公告)日：2021-05-13

申请号：US17157952

申请日：2021-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

公开(公告)号：US09966434B2

公开(公告)日：2018-05-08

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/36 ,  H01L21/265 ,  H01L21/324 ,  H01L29/167 ,  H01L21/283 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US09543408B1

公开(公告)日：2017-01-10

申请号：US14835730

申请日：2015-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Hui Lin ,  Keng-Jen Lin ,  Chun-Yao Yang ,  Yu-Ren Wang

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/3213 ,  H01L21/3215

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/32055 ,  H01L21/32139 ,  H01L21/32155 ,  H01L21/324 ,  H01L23/544 ,  H01L29/66795 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the semiconductor substrate. An implantation process is performed on the amorphous silicon layer. An annealing treatment is performed on the amorphous silicon layer after the implantation process. A patterned hard mask layer is formed on the amorphous silicon layer after the annealing treatment.

Abstract translation: 形成图案化掩模掩模层的方法包括以下步骤。 提供半导体衬底。 在半导体衬底上形成非晶硅层。 对非晶硅层进行注入工艺。 在植入处理之后对非晶硅层进行退火处理。 在退火处理之后，在非晶硅层上形成图案化的硬掩模层。

公开(公告)号：US20130337622A1

公开(公告)日：2013-12-19

申请号：US13971763

申请日：2013-08-20

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

IPC: H01L49/02

CPC classification number: H01L28/24 ,  H01L21/26593 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/0629 ,  H01L28/20

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Abstract translation: 提供半导体工艺，包括以下步骤。 在基板上形成多晶硅层。 对多晶硅层进行不对称双面加热处理，其中用于正面加热的功率不同于用于背面加热的功率。

公开(公告)号：US11950431B2

公开(公告)日：2024-04-02

申请号：US18073574

申请日：2022-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/14 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/552 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H01L23/552 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.