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公开(公告)号：US12176800B2
公开(公告)日：2024-12-24
申请号：US18081706
申请日：2022-12-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hsiu-Ming Yeh , Min-Chia Wang
Abstract: A current generator includes a startup circuit and a bandgap reference circuit coupled to the startup circuit. The startup circuit is for generating a first voltage. The bandgap reference circuit is for generating a second voltage. The bandgap reference circuit includes an operational amplifier. The operational amplifier includes a bias source circuit and a bias generator circuit. The bias source circuit is for generating a reference current according to the first voltage and the second voltage. The bias generator circuit is for generating bias voltages according to the reference current. The startup circuit and the bandgap reference circuit receive a supply voltage.
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公开(公告)号：US20240154512A1
公开(公告)日：2024-05-09
申请号：US18081706
申请日：2022-12-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hsiu-Ming Yeh , Min-Chia Wang
CPC classification number: H02M1/0003 , H02M3/155
Abstract: A current generator includes a startup circuit and a bandgap reference circuit coupled to the startup circuit. The startup circuit is for generating a first voltage. The bandgap reference circuit is for generating a second voltage. The bandgap reference circuit includes an operational amplifier. The operational amplifier includes a bias source circuit and a bias generator circuit. The bias source circuit is for generating a reference current according to the first voltage and the second voltage. The bias generator circuit is for generating bias voltages according to the reference current. The startup circuit and the bandgap reference circuit receive a supply voltage.
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公开(公告)号：US20200186086A1
公开(公告)日：2020-06-11
申请号：US16234593
申请日：2018-12-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ke-Han Chen , Min-Chia Wang
Abstract: A self-biased amplifier includes a capacitor, a bias generation circuit and a common source amplifier. The capacitor is used to receive an input voltage and output an alternating component of the input voltage. The bias generation circuit is coupled to the capacitor, and used to generate a first bias voltage according to the alternating component. The common source amplifier is coupled to the bias generation circuit, and used to generate an amplified voltage according to the first bias voltage.
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公开(公告)号：US10804849B2
公开(公告)日：2020-10-13
申请号：US16234593
申请日：2018-12-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ke-Han Chen , Min-Chia Wang
Abstract: A self-biased amplifier includes a capacitor, a bias generation circuit and a common source amplifier. The capacitor is used to receive an input voltage and output an alternating component of the input voltage. The bias generation circuit is coupled to the capacitor, and used to generate a first bias voltage according to the alternating component. The common source amplifier is coupled to the bias generation circuit, and used to generate an amplified voltage according to the first bias voltage.
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公开(公告)号：US09159668B2
公开(公告)日：2015-10-13
申请号：US14154679
申请日：2014-01-14
Applicant: United Microelectronics Corp.
Inventor： Min-Chia Wang
IPC: H01H85/00 , H01L23/525 , H01L21/66
CPC classification number: H01L23/5256 , G11C17/16 , H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
Abstract: An electronic-fuse (e-fuse) circuit includes: an e-fuse array; a control switch, coupled to the e-fuse array, for controlling whether a voltage supply is applied to the e-fuse array in programming; and a close loop feedback circuit, coupled to the control switch and the e-fuse array, for clamping at lease one node voltage of the e-fuse array to a reference voltage, and for controlling the control switch to control a blowing current in programming the e-fuse array.
Abstract translation: 电子熔丝（e-fuse）电路包括：电子熔丝阵列; 耦合到电子熔丝阵列的控制开关，用于控制在编程中是否向电子熔丝阵列施加电压供应; 以及耦合到控制开关和电子熔丝阵列的闭环反馈电路，用于将电子熔丝阵列的至少一个节点电压钳位到参考电压，并且用于控制控制开关以控制编程中的吹风电流 电子熔丝阵列。
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Patent Agency Ranking
公开(公告)号：US20150200161A1
公开(公告)日：2015-07-16
申请号：US14154679
申请日：2014-01-14
Applicant: United Microelectronics Corp.
Inventor： Min-Chia Wang
IPC: H01L23/525 , H01L21/66
CPC classification number: H01L23/5256 , G11C17/16 , H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
Abstract: An electronic-fuse (e-fuse) circuit includes: an e-fuse array; a control switch, coupled to the e-fuse array, for controlling whether a voltage supply is applied to the e-fuse array in programming; and a close loop feedback circuit, coupled to the control switch and the e-fuse array, for clamping at lease one node voltage of the e-fuse array to a reference voltage, and for controlling the control switch to control a blowing current in programming the e-fuse array.
Abstract translation: 电子熔丝（e-fuse）电路包括：电子熔丝阵列; 耦合到电子熔丝阵列的控制开关，用于控制在编程中是否向电子熔丝阵列施加电压供应; 以及耦合到控制开关和电子熔丝阵列的闭环反馈电路，用于将电子熔丝阵列的至少一个节点电压钳位到参考电压，并且用于控制控制开关以控制编程中的吹风电流 电子熔丝阵列。
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公开(公告)号：US20230178128A1
公开(公告)日：2023-06-08
申请号：US17568727
申请日：2022-01-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Wei Ho , Min-Chia Wang , Hsiu-Ming Yeh , Chung-Ming Lin
IPC: G11C8/08
CPC classification number: G11C8/08
Abstract: A word line driving circuit includes a first circuit and a second circuit. The first circuit is configured to provide a first word line driving voltage and a second word line driving voltage based on a first control signal, a second control signal, a first bias voltage, a second bias voltage and a base voltage. The second circuit is configured to provide the first control signal and the second control signal based on a third control signal, a fourth control signal, a word line control signal, a reverse word line control signal, the first bias voltage, the second bias voltage and the base voltage. The first bias voltage and the second bias voltage have different levels during the read mode and the program mode for adaptively adjusting the read voltage and the program voltage, thereby improving the data access time.
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公开(公告)号：US10658976B1
公开(公告)日：2020-05-19
申请号：US16421492
申请日：2019-05-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ke-Han Chen , Min-Chia Wang
Abstract: A crystal oscillator with a configuration that allows for reduction of power consumption includes a crystal element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a crystal element. The crystal element includes a first terminal coupled to a control terminal of the seventh transistor and a second terminal coupled to a first terminal of the seventh transistor. The second transistor includes a control terminal coupled to an output terminal of the crystal oscillator and a first terminal of the ninth transistor.
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公开(公告)号：US11810643B2
公开(公告)日：2023-11-07
申请号：US17568727
申请日：2022-01-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Wei Ho , Min-Chia Wang , Hsiu-Ming Yeh , Chung-Ming Lin
CPC classification number: G11C8/08
Abstract: A word line driving circuit includes a first circuit and a second circuit. The first circuit is configured to provide a first word line driving voltage and a second word line driving voltage based on a first control signal, a second control signal, a first bias voltage, a second bias voltage and a base voltage. The second circuit is configured to provide the first control signal and the second control signal based on a third control signal, a fourth control signal, a word line control signal, a reverse word line control signal, the first bias voltage, the second bias voltage and the base voltage. The first bias voltage and the second bias voltage have different levels during the read mode and the program mode for adaptively adjusting the read voltage and the program voltage, thereby improving the data access time.
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公开(公告)号：US10177763B1
公开(公告)日：2019-01-08
申请号：US15877368
申请日：2018-01-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Min-Chia Wang
IPC: H03K19/00 , H03K19/0185 , H03K3/356
Abstract: A level shift circuit receives an first input logic signal and a second input logic signal, and generates a first output logic signal and a second output logic signal. The level shift circuit includes a first current mirror module, a second current mirror module, and a latch module. The first current mirror module and the second current mirror module respectively output a first control logic signal having a phase performance following the first input logic signal and a second control logic signal having a phase performance following the second input logic signal. The latch module is coupled to the first current mirror module and the second current mirror module. The latch module receives the first control logic signal and the second control logic signal, and updates correspondingly and stores the output logic signal and the complementary output logic signal.
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