公开(公告)号：US20250056868A1

公开(公告)日：2025-02-13

申请号：US18460605

申请日：2023-09-04

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Tsai ,  Wei Hsuan Chang ,  Chin-Chia Kuo

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device is provided. Recesses are formed in a substrate. A first gate dielectric material is formed on the substrate and filled in the recesses. The first gate dielectric material on the substrate between the recesses is at least partially removed to form a trench. A second gate dielectric material is formed in the trench. A gate conductive layer is formed on the second gate dielectric material. Spacers are formed on sidewalls of the gate conductive layer. A portion of the first gate dielectric material is removed. The remaining first gate dielectric material and the second gate dielectric layer form a gate dielectric layer. The gate dielectric layer includes a body part and a first hump part at a first edge of the body part. The first hump part is thicker than the body part. Doped regions are formed in the substrate beside the spacers.

公开(公告)号：US20240038684A1

公开(公告)日：2024-02-01

申请号：US17889389

申请日：2022-08-16

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Tsai ,  Hao Ping Yan ,  Chin-Chia Kuo ,  Wei Hsuan Chang

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/544 ,  H01L23/564 ,  H01L23/585 ,  H01L2223/5446 ,  H01L2223/54426

Abstract: A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.

公开(公告)号：US20230335609A1

公开(公告)日：2023-10-19

申请号：US17736071

申请日：2022-05-03

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Tsai ,  Wei Hsuan Chang ,  Chin-Chia Kuo

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/8234

CPC classification number: H01L29/42368 ,  H01L29/401 ,  H01L21/823462 ,  H01L27/088

Abstract: The invention provides a transistor structure and a manufacturing method thereof. The transistor structure includes a substrate, a first gate, a second gate, a first gate dielectric layer, and a second gate dielectric layer. The first gate and the second gate are located on the substrate. The first gate dielectric layer is located between the first gate and the substrate. The first gate dielectric layer has a single thickness. The second gate dielectric layer is located between the second gate and the substrate. The second gate dielectric layer has a plurality of thicknesses. A maximum thickness of the first gate dielectric layer is the same as a maximum thickness of the second gate dielectric layer. The transistor structure may reduce process complexity.