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    HIGH-VOLTAGE TRANSISTOR, LEVEL-UP SHIFTING CIRCUIT, AND SEMICONDUCTOR DEVICE
    1.
    发明公开
    HIGH-VOLTAGE TRANSISTOR, LEVEL-UP SHIFTING CIRCUIT, AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240222455A1

    公开(公告)日：2024-07-04

    申请号：US18107516

    申请日：2023-02-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

    IPC: H01L29/423 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

    CPC classification number: H01L29/42368 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/7816 ,  H01L29/41725

    Abstract: A high-voltage transistor includes a well region disposed in a semiconductor substrate, a gate structure disposed above the well region, a gate oxide layer disposed between the gate structure and the well region, a first drift region, and a second drift region. A first portion of the gate oxide layer is thicker than a second portion of the gate oxide layer. A thickness of the second portion is greater than or equal to one eighth of a thickness of the first portion. The first drift region and the second drift region are disposed in the well region, at least partially located at two opposite sides of the gate structure, respectively, and disposed adjacent to the first portion and the second portion, respectively. A conductivity type of the first drift region is identical to that of the second drift region. A level-up shifting circuit includes the high-voltage transistor described above.

    Semiconductor structure
    2.
    发明申请
    Semiconductor structure 有权

    公开(公告)号：US20230006062A1

    公开(公告)日：2023-01-05

    申请号：US17366053

    申请日：2021-07-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

    IPC: H01L29/78 ,  H01L29/45

    Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.

    Method for fabricating merging semiconductor integrated circuit
    4.
    发明授权
    Method for fabricating merging semiconductor integrated circuit 有权

    公开(公告)号：US10177165B1

    公开(公告)日：2019-01-08

    申请号：US15641560

    申请日：2017-07-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ping-Chia Shih ,  Chun-Yao Wang ,  Ming-Hua Tsai ,  Wan-Chun Liao

    IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/266 ,  H01L21/28 ,  H01L29/51

    Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250056868A1

    公开(公告)日：2025-02-13

    申请号：US18460605

    申请日：2023-09-04

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Hua Tsai ,  Wei Hsuan Chang ,  Chin-Chia Kuo

    IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

    Abstract: A method of fabricating a semiconductor device is provided. Recesses are formed in a substrate. A first gate dielectric material is formed on the substrate and filled in the recesses. The first gate dielectric material on the substrate between the recesses is at least partially removed to form a trench. A second gate dielectric material is formed in the trench. A gate conductive layer is formed on the second gate dielectric material. Spacers are formed on sidewalls of the gate conductive layer. A portion of the first gate dielectric material is removed. The remaining first gate dielectric material and the second gate dielectric layer form a gate dielectric layer. The gate dielectric layer includes a body part and a first hump part at a first edge of the body part. The first hump part is thicker than the body part. Doped regions are formed in the substrate beside the spacers.

    Semiconductor structure
    7.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US11569380B2

    公开(公告)日：2023-01-31

    申请号：US17366053

    申请日：2021-07-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

    IPC: H01L29/78 ,  H01L29/45

    Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210366843A1

    公开(公告)日：2021-11-25

    申请号：US17394394

    申请日：2021-08-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

    IPC: H01L23/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/762 ,  H01L27/06 ,  H01L27/08

    Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.

    High voltage MOS structure and its manufacturing method
    10.
    发明授权
    High voltage MOS structure and its manufacturing method 有权

    公开(公告)号：US10141398B1

    公开(公告)日：2018-11-27

    申请号：US15844942

    申请日：2017-12-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ming-Hua Tsai ,  Jung Han ,  Chin-Chia Kuo ,  Wen-Fang Lee ,  Chih-Chung Wang

    IPC: H01L27/118 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49

    Abstract: A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.

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