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公开(公告)号：US20250072080A1
公开(公告)日：2025-02-27
申请号：US18372684
申请日：2023-09-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Yih Chen , Yi-Wen Chen , Chia-Chen Sun , Wei-Chung Sun , Wan-Ching Lee
IPC: H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/08
Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer on the gate structure, forming a patterned mask on the gate structure and one side of the gate structure, removing the first spacer on another side of the gate structure, and then forming a source/drain region adjacent to two sides of the gate structure.
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公开(公告)号：US20250017003A1
公开(公告)日：2025-01-09
申请号：US18230174
申请日：2023-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Yih Chen , Yi-Wen Chen , Wei-Chung Sun
Abstract: A method for physically unclonable function through gate height tuning is provided in the present invention, including steps of forming a high-k dielectric layer and a dummy silicon layer on a semiconductor substrate, removing the dummy silicon layer, forming a work function layer and a metal filling layer on the high-k dielectric layer, and performing a CMP process to remove the metal filling layer, so as to form metal gates with heights lower than a critical gate height, and using the metal gates to manufacture PIO pairs in an internal bias generator. Since the height of metal gates is lower than the critical gate height, a local threshold voltage mismatching of the programmed I/O (PIO) pairs becomes larger, so as to achieve random code generation in physically unclonable function (PUF).
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公开(公告)号：US20230369460A1
公开(公告)日：2023-11-16
申请号：US17835977
申请日：2022-06-09
Applicant: United Microelectronics Corp.
Inventor： Kuang-Hsiu Chen , Wei-Chung Sun , Chao Nan Chen , Chun-Wei Yu , Kuan Hsuan Ku , Shao-Wei Wang
IPC: H01L29/66
CPC classification number: H01L29/66636 , H01L29/66575 , H01L29/66446 , H01L29/66795
Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.
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公开(公告)号：US20250072060A1
公开(公告)日：2025-02-27
申请号：US18943871
申请日：2024-11-11
Applicant: United Microelectronics Corp.
Inventor： Kuang-Hsiu Chen , Wei-Chung Sun , Chao Nan Chen , Chun-Wei Yu , Kuan Hsuan Ku , Shao-Wei Wang
IPC: H01L29/66
Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.
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