公开(公告)号：US20190280106A1

公开(公告)日：2019-09-12

申请号：US16404749

申请日：2019-05-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Yi-Liang Ye ,  Sung-Yuan Tsai ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Zhen Wu ,  Tai-Yen Lin

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/285 ,  H01L29/08 ,  H01L29/78 ,  H01L21/265

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.

公开(公告)号：US10332981B1

公开(公告)日：2019-06-25

申请号：US15943657

申请日：2018-04-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Yi-Liang Ye ,  Sung-Yuan Tsai ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Zhen Wu ,  Tai-Yen Lin

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L21/285 ,  H01L21/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.

公开(公告)号：US10332741B2

公开(公告)日：2019-06-25

申请号：US15590004

申请日：2017-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/66 ,  H01L29/00 ,  H01L21/321

Abstract: A method for post chemical mechanical polishing clean is provided in the present invention, which include the steps of providing a substrate, performing a chemical mechanical polishing process, and performing a plurality of cleaning processes sequentially substrate using solutions of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) with different ratios and at different temperatures.

公开(公告)号：US20190157455A1

公开(公告)日：2019-05-23

申请号：US15820443

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Hsu Ting ,  Chung-Fu Chang ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L21/3105 ,  H01L21/02532 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

公开(公告)号：US20180122707A1

公开(公告)日：2018-05-03

申请号：US15339949

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Wen-Jiun Shen ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.

公开(公告)号：US20170330742A1

公开(公告)日：2017-11-16

申请号：US15636660

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/0206 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.

公开(公告)号：US09741572B1

公开(公告)日：2017-08-22

申请号：US15049152

申请日：2016-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Chun-Wei Yu ,  Yu-Ying Lin ,  Yu-Ren Wang

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28185 ,  H01L21/28167 ,  H01L21/823462 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.

公开(公告)号：US20230352587A1

公开(公告)日：2023-11-02

申请号：US18218098

申请日：2023-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66575 ,  H01L29/6656 ,  H01L29/6653 ,  H01L29/42364

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

公开(公告)号：US10700202B2

公开(公告)日：2020-06-30

申请号：US16172856

申请日：2018-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Chao-Nan Chen ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.

公开(公告)号：US20200052123A1

公开(公告)日：2020-02-13

申请号：US16056540

申请日：2018-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Hao-Hsuan Chang ,  Chia-Wei Hsu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762

Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.