公开(公告)号：US20210257249A1

公开(公告)日：2021-08-19

申请号：US16820730

申请日：2020-03-17

Applicant: United Semiconductor (Xiamen) Co., Ltd.

Inventor： Long Wang ,  Zijun Sun ,  Chin-Chun Huang ,  Hailong Gu ,  Penghui Lu ,  WEN YI TAN

IPC: H01L21/762 ,  H01L21/768

Abstract: A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation.

公开(公告)号：US11107723B1

公开(公告)日：2021-08-31

申请号：US16820730

申请日：2020-03-17

Applicant: United Semiconductor (Xiamen) Co., Ltd.

Inventor： Long Wang ,  Zijun Sun ,  Chin-Chun Huang ,  Hailong Gu ,  Penghui Lu ,  Wen Yi Tan

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/768

Abstract: A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation.