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公开(公告)号：US12219886B2
公开(公告)日：2025-02-04
申请号：US17388027
申请日：2021-07-29
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： Shuzhi Zou , Dejin Kong , Xiang Bo Kong , Chin-Chun Huang , Wen Yi Tan
Abstract: A resistive memory device includes a stacked structure and a copper via conductor structure. The stacked structure includes a first electrode, a second electrode, and a variable resistance layer. The second electrode is disposed above the first electrode in a vertical direction, and the variable resistance layer is disposed between the first electrode and the second electrode in the vertical direction. The copper via conductor structure is disposed under the stacked structure. The first electrode includes a tantalum nitride layer directly connected with the copper via conductor structure.
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公开(公告)号：US20230260857A1
公开(公告)日：2023-08-17
申请号：US17699197
申请日：2022-03-21
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： LINSHAN YUAN , Yi Lu Dai , Guang Yang , JINJIAN OUYANG , Hang Liu , Chin-Chun Huang , WEN YI TAN
CPC classification number: H01L22/34 , G01R31/2884
Abstract: The invention provides a semiconductor testkey, which comprises a testkey on a substrate, the testkey comprises a first resistor pattern, a second resistor pattern and a third resistor pattern arranged in a strip, the distance between the first resistor pattern and the second resistor pattern is defined as a first distance, and the distance between the second resistor pattern and the third resistor pattern is defined as a second distance, the first resistor pattern, the second resistor pattern and the third resistor pattern have the same pattern, and the second distance is larger than the first distance.
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3.发明申请公开(公告)号：US20220148770A1
公开(公告)日：2022-05-12
申请号：US17115803
申请日：2020-12-09
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： Wei-Chun Chang , Yunfei Fu , You-Di Jhang , Chin-Chun Huang , WEN YI TAN
IPC: H01C17/075 , H01C7/00 , C23C16/04 , C23C16/34 , C23C16/505
Abstract: The invention provides a method for adjusting the resistance value of a thin film resistor layer in a semiconductor structure, which comprises forming the thin film resistor layer, the material of the thin film resistor layer comprises titanium nitride, and the thin film resistor layer has an original resistance value, a mask layer with tensile force is formed above the thin film resistor layer, and the mask layer with tensile force changes a lattice size of the thin film resistor layer, so that the lattice size of the thin film resistor layer becomes larger and the original resistance value of the thin film resistor layer is reduced.
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4.发明授权公开(公告)号：US11201116B2
公开(公告)日：2021-12-14
申请号：US16843903
申请日：2020-04-09
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： Bin Guo , Hailong Gu , Chin-Chun Huang , Wen Yi Tan
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H01L21/321
Abstract: A method for fabricating semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate, patterning the first IMD layer to form first IMD patterns on the substrate, a trench surrounding the first IMD patterns, and a second IMD pattern surrounding the trench, forming a metal layer in the trench to surround the first IMD patterns, forming a second IMD layer on the first IMD patterns, the metal layer, and the second IMD pattern, and forming via conductors in the second IMD layer. Preferably, the via conductors not overlapping the first IMD patterns.
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公开(公告)号：US11107723B1
公开(公告)日：2021-08-31
申请号：US16820730
申请日：2020-03-17
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： Long Wang , Zijun Sun , Chin-Chun Huang , Hailong Gu , Penghui Lu , Wen Yi Tan
IPC: H01L21/70 , H01L21/762 , H01L21/768
Abstract: A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20200185456A1
公开(公告)日：2020-06-11
申请号：US16231615
申请日：2018-12-24
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： Chin-Chun Huang , Yun-Pin Teng , You-Di Jhang , WEN YI TAN
Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.
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公开(公告)号：US20250072077A1
公开(公告)日：2025-02-27
申请号：US18370392
申请日：2023-09-19
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： Wei-Chun Chang , You-Di Jhang , Han-Min Huang , Chin-Chun Huang , WEN YI TAN
Abstract: A semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a metal gate structure, at least one dummy body, two source/drain regions, and a dielectric layer. The metal gate structure is disposed on the substrate. The at least one dummy body is disposed within the metal gate structure. The source/drain regions are disposed at two sides of the metal gate structure respectively in the substrate. The dielectric layer is disposed on the substrate, around the metal gate structure.
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公开(公告)号：US20240112323A1
公开(公告)日：2024-04-04
申请号：US17988785
申请日：2022-11-17
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： Yu Peng Hong , QINGRONG CHEN , Kai Ping Huang , Chin-Chun Huang , WEN YI TAN
CPC classification number: G06T7/001 , G01N21/9501 , G06T7/0006 , G06T2207/10061 , G06T2207/30148
Abstract: A method for detecting defects on a wafer including the steps of obtaining a reference image of a chip pattern formed on a reference wafer, using a computer algorithm to analyze the reference image to produce a division map for the chip pattern; setting respective thresholds for divisions of the division map, obtaining a comparison data between a test image of the chip pattern formed on a test wafer and the reference image, using the division map and the thresholds to examine the comparison data to identify a defect in the test image.
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公开(公告)号：US20210257249A1
公开(公告)日：2021-08-19
申请号：US16820730
申请日：2020-03-17
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： Long Wang , Zijun Sun , Chin-Chun Huang , Hailong Gu , Penghui Lu , WEN YI TAN
IPC: H01L21/762 , H01L21/768
Abstract: A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation.
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公开(公告)号：US10937830B2
公开(公告)日：2021-03-02
申请号：US16868495
申请日：2020-05-06
Applicant: United Semiconductor (Xiamen) Co., Ltd.
Inventor： Chin-Chun Huang , Yun-Pin Teng , You-Di Jhang , Wen Yi Tan
Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.
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