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公开(公告)号：US20240184281A1
公开(公告)日：2024-06-06
申请号：US18104777
申请日：2023-02-01
发明人： Qun Feng Liu , Fujin Wang , Kai Ping Huang , Wen Yi Tan
CPC分类号： G05B23/0283 , G01M99/005
摘要： A machine monitoring system includes a plurality of first machines and a control module. The first machines are for a first process. The control module is connected with the first machines. The control module is configured to: define each of the first machines as a high-risk first machine or a low-risk first machine according to a first risk score of each of the first machines; designate one of the first machines being defined as the high-risk first machine as a selected high-risk first machine; assign an object to be processed by the first process through the selected high-risk first machine to obtain a processed object; and determine whether to continue or stop to use the selected high-risk first machine according to a test result of the processed object.
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公开(公告)号：US20230384678A1
公开(公告)日：2023-11-30
申请号：US17844750
申请日：2022-06-21
发明人： Chien-Chung Tsai , QingZhang Zhang , WEN YI TAN
摘要： The invention provides a semiconductor manufacturing method, which comprises providing a substrate with a photoresist layer, forming a hydrophilic film on a surface of the photoresist layer by a spin coating process, and forming a top anti-reflective coating (TARC) on the surface of the hydrophilic film.
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公开(公告)号：US20230352347A1
公开(公告)日：2023-11-02
申请号：US17752869
申请日：2022-05-25
发明人： LINSHAN YUAN , Guang Yang , YUCHUN GUO , JINJIAN OUYANG , Chin-Chun Huang , WEN YI TAN
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823871 , H01L27/092
摘要： A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.
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公开(公告)号：US11804403B2
公开(公告)日：2023-10-31
申请号：US17382379
申请日：2021-07-22
发明人： Ji He Huang , Wen Yi Tan
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L21/7682 , H01L21/76819 , H01L21/76835 , H01L23/5283 , H01L23/53295
摘要： A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.
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公开(公告)号：US20230345848A1
公开(公告)日：2023-10-26
申请号：US18218570
申请日：2023-07-05
发明人： Dejin KONG , Jinjian OUYANG , Xiang Bo KONG , Wen Yi TAN
CPC分类号： H10N70/841 , H10B63/80 , H10N70/021 , H10N70/066 , H10N70/068 , H10N70/8833
摘要： A resistive random access memory includes a first dielectric layer, a bottom electrode on the first dielectric layer, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer, a second dielectric layer on the first dielectric layer and around the variable-resistance layer and the bottom electrode, and a spacer on the bottom electrode and inserting between the variable-resistance layer and the second dielectric layer.
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公开(公告)号：US20230245934A1
公开(公告)日：2023-08-03
申请号：US17709392
申请日：2022-03-30
发明人： Zhi Xiang Qiu , RONG HE , Hailong Gu , Chin-Chun Huang , WEN YI TAN
IPC分类号： H01L21/66
CPC分类号： H01L22/34
摘要： A testkey structure for semiconductor device includes a substrate, a gate structure disposed on the substrate, and a plurality of first dummy gate structures disposed on the substrate and arranged around the gate structure. A bottom surface of the gate structure is lower than bottom surfaces of the first dummy gate structures. A top surface of the gate structure is flush with top surfaces of the first dummy gate structures.
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公开(公告)号：US11610821B2
公开(公告)日：2023-03-21
申请号：US17381164
申请日：2021-07-20
发明人： Rui Ju , Wen Yi Tan
IPC分类号： H01L29/10 , H01L29/78 , H01L21/8238 , H01L21/28
摘要： A method of forming semiconductor device is disclosed. A substrate having a logic circuit region and a memory cell region is provided. A first transistor with a first gate is formed in the logic circuit region and a second transistor with a second gate is formed in the memory cell region. A stressor layer is deposited to cover the first transistor in the logic circuit region and the second transistor in the memory cell region. The first transistor and the second transistor are subjected to an annealing process under the influence of the stressor layer to recrystallize the first gate and the second gate.
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公开(公告)号：US20230030500A1
公开(公告)日：2023-02-02
申请号：US17408481
申请日：2021-08-22
发明人： MAOHUA REN , Yuan-Chi Pai , WEN YI TAN
摘要： A reticle thermal expansion calibration method includes exposing a group of wafers and generating a sub-recipe, performing data mining and data parsing to generate a plurality of overlay parameters, extracting a plurality of predetermined parameters from the plurality of overlay parameters, performing a linear regression on each of the predetermined parameters, and generating a coefficient of determination for each of the predetermined parameters.
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公开(公告)号：US20220399226A1
公开(公告)日：2022-12-15
申请号：US17382379
申请日：2021-07-22
发明人： Ji He Huang , WEN YI TAN
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532
摘要： A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.
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公开(公告)号：US11527438B2
公开(公告)日：2022-12-13
申请号：US17109108
申请日：2020-12-01
发明人： Xiongwu He , Weiguo Xu , Yuan-Chi Pai , Wen Yi Tan
IPC分类号： H01L21/768 , G03F1/42 , G03F1/86 , G03F7/20 , H01L21/311 , H01L21/66
摘要： A manufacturing method of a contact structure includes the following steps. A substrate is provided, and the substrate includes a first region and a second region. A dielectric layer is formed on the substrate. A photoresist layer is formed on the dielectric layer. An exposure process is performed. The exposure process includes first exposure steps and second exposure steps. Each of the first exposure steps is performed to a part of the first region of the substrate. Each of the second exposure steps is performed to a part of the second region of the substrate. Each of the second exposure steps is performed with a first overlay shift by a first predetermined distance. A develop process is performed for forming openings in the photoresist layer.
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