公开(公告)号：US20250107137A1

公开(公告)日：2025-03-27

申请号：US18398222

申请日：2023-12-28

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Jiawei WANG ,  Dingxiang MA ,  Yue GAO ,  Gen LIU ,  Shengduo WANG ,  Yuanqing YE ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: A lateral power semiconductor device layout and a device structure belong to the technical field of power semiconductor devices. A method for designing a lateral power semiconductor device layout with high integrity and high cell density has the following advantages of reducing a specific on-resistance of the device, increasing a width of a channel per unit area, improving the current capability of the device, optimizing the static characteristic of the device, reducing the area of a drain region and the parasitic capacitance of the device, reducing the delay time of a cell switch caused by an excessively long gate electrode of a traditional finger cell, optimizing the dynamic characteristic of the device, optimizing the cell edge of the device and the curvature effect of a terminal, and reducing the pre-breakdown risk of the device.