公开(公告)号：US11062072B1

公开(公告)日：2021-07-13

申请号：US16912006

申请日：2020-06-25

Applicant: University of Electronic Science and Technology of China

Inventor： Yuehang Xu ,  Shuman Mao ,  Yunqiu Wu

IPC: G06F30/30 ,  G06F30/367 ,  G06F30/373 ,  G06F119/22 ,  G06F119/06

Abstract: A yield load pull system-based integrated circuit design method and a system thereof are provided. The method includes: setting a yield-related threshold; setting a source impedance; configuring a sweep range of a Smith chart; determining load impedance points within the sweep range of the Smith chart; acquiring impedance information; determining output characteristics of a plurality of sample devices at each load impedance point of the determined load impedance points, based on the source impedance and the impedance information corresponding to each load impedance point, by invoking a harmonic balance simulator embedded in an Advanced Design System, where the output characteristics comprise: a large-signal gain, an output power and a power-added efficiency; determining a device yield for each load impedance point; for each output characteristic calculating a mean value across the plurality of sample devices, at each load impedance point; and determining a best load impedance; conducting IC design.