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1.发明授权公开(公告)号：US11611429B2
公开(公告)日：2023-03-21
申请号：US16309397
申请日：2017-06-14
摘要： Methods and integrated circuit architectures for assuring the protection of intellectual property between third party IP providers, system designers (e.g., SoC designers), fabrication entities, and assembly entities are provided. Novel design flows for the prevention of IP overuse, IP piracy, and IC overproduction are also provided. A comprehensive framework for forward trust between 3PIP vendors, SoC design houses, fabrication entities, and assembly entities can be achieved, and the unwanted modification of IP can be prevented.
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公开(公告)号：US11270002B2
公开(公告)日：2022-03-08
申请号：US15978734
申请日：2018-05-14
摘要： Disclosed are various embodiments for detecting hardware Trojans through information flow security verification. A file comprising register transfer level (HDL) code for an intellectual property core is loaded from memory. An asset within the intellectual property core is identified. An integrity verification or confidentiality verification of the HDL code that represents the asset is performed. An integrity violation or confidentiality violation within the HDL code as a result of performance of the integrity verification or confidentiality violation on the HDL code that represents the asset is detected. A malicious control point or a malicious observation point linked to the asset is identified. Finally, a trigger circuit for a hardware Trojan is identified in response to identification of the malicious control point or malicious observation point.
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公开(公告)号：US11475168B2
公开(公告)日：2022-10-18
申请号：US16520002
申请日：2019-07-23
IPC分类号： G06F21/75 , G06F30/30 , G06F30/34 , G06F119/06
摘要： Various examples are provided related to power side-channel vulnerability assessment. In one example, a method includes identifying target registers in an IC design; generating input patterns associated with a target function that can generate a power difference in the target registers when processing the target function; determining a side-channel vulnerability (SCV) metric using the power difference produced by the input patterns; and identifying a vulnerability in the IC design using the SCV metric. Identification of the vulnerability allows for modification of the IC design at an early stage, which can avoid power side-channel attacks (e.g., DPA and CPA) in the fabricated IC design. The method can be used for pre-silicon power side-channel leakage assessment of IC designs such as, e.g., cryptographic and non-cryptographic circuits.
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公开(公告)号：US11087058B1
公开(公告)日：2021-08-10
申请号：US16745744
申请日：2020-01-17
发明人： Domenic J. Forte , Mark M. Tehranipoor , Qihang Shi , Huanyu Wang , Haoting Shen
摘要： Embodiments of systems and methods for an FIB-aware anti-probing physical design flow are described in the present disclosure. Such embodiments incorporate new and improved security-critical steps in a physical design flow, in which the design is constrained to provide coverage on asset nets through an internal shield.
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公开(公告)号：US11030737B2
公开(公告)日：2021-06-08
申请号：US16573922
申请日：2019-09-17
发明人： Mark M. Tehranipoor , Haoting Shen , Nidish Vashistha , Navid Asadizanjani , Mir Tanjidur Rahman , Damon Woodard
摘要： A method of detecting hardware Trojans in an IC includes providing a golden IC layout data set or SEM image data taken at long dwelling time on an active area of the golden IC after polishing it from the backside. Next, the IC under authentication (IUA) sample is prepared for fast SEM imagining (shorter dwelling time) after backside thinning. Next step is to perform image processing on the IUA's SEM image, which includes histogram equalization with noise filtering using Gaussian and Median filters. In the last step, the IUA sample data with the shorter dwelling time is compared with the golden IC layout data or the golden image data from high quality (longer dwelling time) SEM scanning process. At the end the result of the comparison is used to identify hardware Trojans.
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公开(公告)号：US20200090325A1
公开(公告)日：2020-03-19
申请号：US16573922
申请日：2019-09-17
发明人： Mark M. Tehranipoor , Haoting Shen , Nidish Vashistha , Navid Asadizanjani , Mir Tanjidur Rahman , Damon Woodard
摘要： A method of detecting hardware Trojans in an IC includes providing a golden IC layout data set or SEM image data taken at long dwelling time on an active area of the golden IC after polishing it from the backside. Next, the IC under authentication (IUA) sample is prepared for fast SEM imagining (shorter dwelling time) after backside thinning. Next step is to perform image processing on the IUA's SEM image, which includes histogram equalization with noise filtering using Gaussian and Median filters. In the last step, the IUA sample data with the shorter dwelling time is compared with the golden IC layout data or the golden image data from high quality (longer dwelling time) SEM scanning process. At the end the result of the comparison is used to identify hardware Trojans.
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公开(公告)号：US20200065456A1
公开(公告)日：2020-02-27
申请号：US16535795
申请日：2019-08-08
发明人： Mark M. Tehranipoor , Domenic J. Forte , Farimah Farahmandi , Adib Nahiyan , Fahim Rahman , Mohammad Sazadur Rahman
IPC分类号： G06F21/14 , H03K19/177 , G06F21/72 , G06F12/14
摘要： A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a φ-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the φ-bit protected Obfuscation Key generated by the LFSR, and output k └φ×α┘-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.
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8.发明申请公开(公告)号：US20190165935A1
公开(公告)日：2019-05-30
申请号：US16309397
申请日：2017-06-14
摘要： Methods and integrated circuit architectures for assuring the protection of intellectual property between third party IP providers, system designers (e.g., SoC designers), fabrication entities, and assembly entities are provided. Novel design flows for the prevention of IP overuse, IP piracy, and IC overproduction are also provided. A comprehensive framework for forward trust between 3PIP vendors, SoC design houses, fabrication entities, and assembly entities can be achieved, and the unwanted modification of IP can be prevented.
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公开(公告)号：US20210026994A1
公开(公告)日：2021-01-28
申请号：US16520002
申请日：2019-07-23
摘要： Various examples are provided related to power side-channel vulnerability assessment. In one example, a method includes identifying target registers in an IC design; generating input patterns associated with a target function that can generate a power difference in the target registers when processing the target function; determining a side-channel vulnerability (SCV) metric using the power difference produced by the input patterns; and identifying a vulnerability in the IC design using the SCV metric. Identification of the vulnerability allows for modification of the IC design at an early stage, which can avoid power side-channel attacks (e.g., DPA and CPA) in the fabricated IC design. The method can be used for pre-silicon power side-channel leakage assessment of IC designs such as, e.g., cryptographic and non-cryptographic circuits.
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