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公开(公告)号：US12282543B2
公开(公告)日：2025-04-22
申请号：US17525176
申请日：2021-11-12
IPC: G06F21/55 , G06F7/58 , G06F15/78 , H04L9/06 , H04L49/109
Abstract: The present disclosure describes digital watermark detection systems and methods. In one such system, a plurality of intellectual property cores are integrated on a system-on-chip, such that the intellectual property cores comprise a first intellectual property core and a second intellectual property core. The system further includes a first network interface connected to the first intellectual property core that can encode a first digital watermark into a packet stream designated for the second intellectual property core. The system further includes a second network interface connected to the second intellectual property core that can receive the packet stream and decode the packet stream to generate a second digital watermark. The second network interface is further configured to perform a validation test on the packet stream and deliver the packet stream to the second intellectual property core when the first digital watermark is determined to match the second digital watermark.
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公开(公告)号：US20220156366A1
公开(公告)日：2022-05-19
申请号：US17525176
申请日：2021-11-12
IPC: G06F21/55 , H04L12/933 , G06F7/58 , G06F15/78 , H04L9/06
Abstract: The present disclosure describes digital watermark detection systems and methods. In one such system, a plurality of intellectual property cores are integrated on a system-on-chip, such that the intellectual property cores comprise a first intellectual property core and a second intellectual property core. The system further includes a first network interface connected to the first intellectual property core that can encode a first digital watermark into a packet stream designated for the second intellectual property core. The system further includes a second network interface connected to the second intellectual property core that can receive the packet stream and decode the packet stream to generate a second digital watermark. The second network interface is further configured to perform a validation test on the packet stream and deliver the packet stream to the second intellectual property core when the first digital watermark is determined to match the second digital watermark.
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公开(公告)号：US11580265B2
公开(公告)日：2023-02-14
申请号：US17085213
申请日：2020-10-30
Inventor： Prabhat Kumar Mishra , Yangdi Lyu
IPC: G06F21/76 , G06F30/3308 , G06F21/56
Abstract: The present disclosure describes various embodiments of systems, apparatuses, and methods for detecting a Trojan inserted integrated circuit design using delay-based side channel analysis. In one such embodiment, an automated test generation algorithm produces test patterns that are likely to activate trigger conditions and change critical paths of an integrated circuit design.
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公开(公告)号：US11568046B2
公开(公告)日：2023-01-31
申请号：US16893701
申请日：2020-06-05
Inventor： Prabhat Kumar Mishra , Yangdi Lyu
IPC: G06F21/55 , G01R31/317
Abstract: An exemplary method for generating a test vector to activate a Trojan triggering condition includes the operations of obtaining a design graph representation of an electronic circuit; constructing a satisfiability graph from the design graph representation, wherein the satisfiability graph includes a set of vertices representing rare signals of the electronic circuit and satisfiability connections between the vertices; finding a plurality of maximal satisfiable cliques in the satisfiability graph, wherein a maximal satisfiable clique corresponds to a triggering condition for a payload of the electronic circuit; generating a test vector for each of the maximal satisfiable cliques; and performing a test for the presence of a hardware Trojan circuit in the electronic circuit using the generated test vectors as input signals.
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公开(公告)号：US11144648B2
公开(公告)日：2021-10-12
申请号：US16358908
申请日：2019-03-20
Inventor： Swarup Bhunia , Jonathan William Cruz , Prabhat Kumar Mishra
Abstract: A method and system for evaluating software tools that detect malicious hardware modifications is provided. In one embodiment, among others, a system comprises a computing device and an application. The application causes the computing device to at least receive hardware description language code that represents a circuit design and calculate a signal probability for one or more nodes in the circuit design. The application also causes the computing device to identify one or more rare nodes in the circuit design and generate a Trojan sample population. The application further causes the computing device to generate a feasible Trojan population and generate a Trojan test instance based at least in part on a random selection from the Trojan feasible population. Additionally, the application causes the computing device to generate modified hardware description code from the Trojan test instance.
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Patent Agency Ranking
公开(公告)号：US12079334B2
公开(公告)日：2024-09-03
申请号：US17543940
申请日：2021-12-07
Inventor： Prabhat Kumar Mishra , Zhixin Pan
CPC classification number: G06F21/554 , G06N20/00 , G06F2221/034
Abstract: The present disclosure provides systems and methods for test pattern generation to detect a hardware Trojan. One such method includes determining, by a computing device, a set of initial test patterns to activate the hardware Trojan within an integrated circuit design; evaluating nodes of the integrated circuit design and assigning a rareness attribute value and a testability attribute value associated with respective nodes of the integrated circuit design; and generating a set of additional test patterns to activate the hardware Trojan within the integrated circuit design using a reinforcement learning model. The set of initial test patterns is applied as an input along with rareness attribute values and testability attribute values associated with the nodes of the integrated circuit, and the reinforcement learning model is trained with a stochastic learning scheme to identify optimal test patterns for triggering nodes of the integrated circuit design.
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7.发明公开公开(公告)号：US20230244819A1
公开(公告)日：2023-08-03
申请号：US17973768
申请日：2022-10-26
Inventor： Prabhat Kumar Mishra , Hansika M. Weerasena Loku Kattadige , Thelijjagoda Subodha Nadeeshan Charles
Abstract: The present disclosure presents systems and methods of secure communication by a system-on-chip. One such method comprises receiving, by a sender of a network-on-chip component of the system-on-chip, a message sequence; transforming, by the sender of the network-on-chip component of the system-on-chip, the message sequence into a pseudo-message sequence with an all-or-nothing transform; performing key-less encryption, by the sender of the network-on-chip component of the system-on-chip, of the pseudo-message sequence to obtain a ciphertext message sequence using a chaffing and winnowing scheme; and transmitting, by the sender of the network-on-chip component of the system-on-chip, the ciphertext message sequence to a receiver of the network-on-chip component of the system-on-chip.
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公开(公告)号：US11579185B2
公开(公告)日：2023-02-14
申请号：US16893696
申请日：2020-06-05
Inventor： Prabhat Kumar Mishra , Yangdi Lyu
IPC: G01R31/28 , G01R31/3185 , G01R31/317 , G06F21/57
Abstract: An exemplary method of detecting a Trojan circuit in an integrated circuit is related to applying a test pattern comprising an initial test pattern followed by a corresponding succeeding test pattern to a golden design of the integrated circuit, wherein a change in the test pattern increases side-channel sensitivity; measuring a side-channel parameter in the golden design of the integrated circuit after application of the test pattern; applying the test pattern to a design of the integrated circuit under test; measuring the side-channel parameter in the design of the integrated circuit under test after application of the test pattern; and determining a Trojan circuit to be present in the integrated circuit under test when the measured side-channel parameters vary by a threshold.
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公开(公告)号：US11552782B2
公开(公告)日：2023-01-10
申请号：US16915021
申请日：2020-06-29
Inventor： Prabhat Kumar Mishra , Thelijjagoda S N Charles , Yangdi Lyu
Abstract: Various examples are provided related to software and hardware architectures that enable a lightweight incremental encryption scheme that is implemented on a System-on-chip (SoC) resource such as a network interface. In one example, among others, a method for incremental encryption includes obtaining, by a network interface (NI) of a sender intellectual property (IP) core in a network-on-chip (NoC) based system-on-chip (SoC) architecture, a payload for communication to a receiver intellectual property (IP) core; identifying, by the NI, one or more different blocks between the payload and a payload of a previous packet communicated between the sender IP core and the receiver IP core; and encrypting, by the NI, the one or more different blocks to create encrypted blocks of an encrypted payload.
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公开(公告)号：US20210021404A1
公开(公告)日：2021-01-21
申请号：US16915021
申请日：2020-06-29
Inventor： Prabhat Kumar Mishra , Thelijjagoda S N Charles , Yangdi Lyu
Abstract: Various examples are provided related to software and hardware architectures that enable a lightweight incremental encryption scheme that is implemented on a System-on-chip (SoC) resource such as a network interface. In one example, among others, a method for incremental encryption includes obtaining, by a network interface (NI) of a sender intellectual property (IP) core in a network-on-chip (NoC) based system-on-chip (SoC) architecture, a payload for communication to a receiver intellectual property (IP) core; identifying, by the NI, one or more different blocks between the payload and a payload of a previous packet communicated between the sender IP core and the receiver IP core; and encrypting, by the NI, the one or more different blocks to create encrypted blocks of an encrypted payload.
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