公开(公告)号：US06237076B1

公开(公告)日：2001-05-22

申请号：US09141892

申请日：1998-08-28

申请人： Ute Gaertner ,  Klaus Jörg Getzlaff ,  Oliver Laub ,  Erwin Pfeffer

发明人： Ute Gaertner ,  Klaus Jörg Getzlaff ,  Oliver Laub ,  Erwin Pfeffer

IPC分类号： G06F1338

CPC分类号： G06F9/30014 ,  G06F9/30043 ,  G06F9/30149 ,  G06F9/384

摘要： A method and system for renaming registers of said system is proposed in which mixed instruction sets, e.g. 32 bit and 64 bit instructions are carried out concurrently in one program. In case of an instruction sequence of a preceding 64 bit instruction and one or more 32 bit instructions to be executed in-order after the 64 bit instruction and where the 32 bit instructions having a data dependence to the preceding 64 bit instruction, said rest of the register range changed by the preceding 64 bit instruction is copied to the corresponding location in a target register of the succeeding 32 bit instruction, at least if the same logical register is specified by the 32 bit instruction as it was specified by the preceding 64 bit instruction. The copy source is addressed by the register number and hold in a list (28).

摘要翻译： 提出了一种用于重命名所述系统的寄存器的方法和系统，其中混合指令集，例如， 在一个程序中同时执行32位和64位指令。 在先前64位指令的指令序列和在64位指令之后按顺序执行的一个或多个32位指令的情况下，其中32位指令与前一个64位指令具有数据依赖关系的情况下， 由前一个64位指令改变的寄存器范围被复制到后续的32位指令的目标寄存器中的对应位置，至少如果由前一个64位指令指定的32位指令指定相同的逻辑寄存器 指令。 复制源由寄存器编号寻址并保存在列表（28）中。

公开(公告)号：US5974543A

公开(公告)日：1999-10-26

申请号：US24691

申请日：1998-02-17

申请人： Rolf Hilgendorf ,  Oliver Laub ,  Hans-Werner Tast

发明人： Rolf Hilgendorf ,  Oliver Laub ,  Hans-Werner Tast

IPC分类号： G06F9/38 ,  G06F9/42 ,  G06F12/0875 ,  G06F9/32

CPC分类号： G06F9/3806 ,  G06F12/0875 ,  G06F9/4426

摘要： An apparatus and a method for performing subroutine call and return operations in a computer having a processor with an instruction prefetch mechanism which includes a branch history table for storing target addresses of a plurality of branch instructions found in an instruction stream. The branch history table 22 contains a potential call instruction tag 37 and a return instruction tag 39. For each potential subroutine call instruction found in a prefetch instruction stream an address pair containing the call target address and the next sequential instruction address of the instruction is stored in a return identification stack 24. Subsequently detected branch instructions initiate an associative search on the next sequential instruction part in the return identification stack where a matching entry identifies the branch instruction as a return instruction. The address pair contained in the matching entry is then transferred to a return cache 30 which is arranged in parallel to the branch history table. The branch history table and the return cache are simultaneously accessed in the same operation cycle with the address 28 of each prefetched instruction, and if by the access a return instruction tag is found, the next sequential instruction address from the return cache is used as return address. A return cache update 32 is performed in response to a branch instruction in the instruction stream by a lookup of the return cache for an entry having a corresponding target address and by replacing the next sequential instruction address in said entry by the next sequential address of said branch instruction.

摘要翻译： 一种在具有具有指令预取机制的处理器的计算机中执行子程序调用和返回操作的装置和方法，该指令预取机制包括用于存储在指令流中发现的多个分支指令的目标地址的分支历史表。 分支历史表22包含潜在的呼叫指令标签37和返回指令标签39.对于在预取指令流中发现的每个潜在的子程序调用指令，存储包含该指令的调用目标地址和下一个顺序指令地址的地址对 随后检测到的分支指令在返回识别堆栈中的下一个顺序指令部分发起关联搜索，其中匹配条目将转移指令标识为返回指令。 然后将包含在匹配条目中的地址对传送到与分支历史表并行布置的返回高速缓存30。 分支历史表和返回缓存在与每个预取指令的地址28相同的操作周期中同时访问，并且如果通过访问返回指令标记被找到，则来自返回高速缓存的下一个顺序指令地址被用作返回 地址。 通过对具有相应目标地址的条目的返回高速缓存的查找来响应于指令流中的分支指令来执行返回高速缓存更新32，并且通过将所述条目中的下一个顺序指令地址替换为所述条目的下一个顺序地址， 分支指令。