公开(公告)号：US06237076B1

公开(公告)日：2001-05-22

申请号：US09141892

申请日：1998-08-28

申请人： Ute Gaertner ,  Klaus Jörg Getzlaff ,  Oliver Laub ,  Erwin Pfeffer

发明人： Ute Gaertner ,  Klaus Jörg Getzlaff ,  Oliver Laub ,  Erwin Pfeffer

IPC分类号： G06F1338

CPC分类号： G06F9/30014 ,  G06F9/30043 ,  G06F9/30149 ,  G06F9/384

摘要： A method and system for renaming registers of said system is proposed in which mixed instruction sets, e.g. 32 bit and 64 bit instructions are carried out concurrently in one program. In case of an instruction sequence of a preceding 64 bit instruction and one or more 32 bit instructions to be executed in-order after the 64 bit instruction and where the 32 bit instructions having a data dependence to the preceding 64 bit instruction, said rest of the register range changed by the preceding 64 bit instruction is copied to the corresponding location in a target register of the succeeding 32 bit instruction, at least if the same logical register is specified by the 32 bit instruction as it was specified by the preceding 64 bit instruction. The copy source is addressed by the register number and hold in a list (28).

摘要翻译： 提出了一种用于重命名所述系统的寄存器的方法和系统，其中混合指令集，例如， 在一个程序中同时执行32位和64位指令。 在先前64位指令的指令序列和在64位指令之后按顺序执行的一个或多个32位指令的情况下，其中32位指令与前一个64位指令具有数据依赖关系的情况下， 由前一个64位指令改变的寄存器范围被复制到后续的32位指令的目标寄存器中的对应位置，至少如果由前一个64位指令指定的32位指令指定相同的逻辑寄存器 指令。 复制源由寄存器编号寻址并保存在列表（28）中。

公开(公告)号：US06766434B2

公开(公告)日：2004-07-20

申请号：US10126239

申请日：2002-04-19

申请人： Ute Gaertner ,  Norbert Hagspiel ,  Frank Lehnert ,  Erwin Pfeffer ,  Kerstin Schelm

发明人： Ute Gaertner ,  Norbert Hagspiel ,  Frank Lehnert ,  Erwin Pfeffer ,  Kerstin Schelm

IPC分类号： G06F1208

CPC分类号： G06F12/1027

摘要： The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).

摘要翻译： 本发明一般涉及诸如IBM ESA / 390或RS / 6000系统的共享存储器多处理器系统，更具体地涉及用于在多个CPU之间共享第二级转换后备缓冲器（TLB 2）的方法和系统（ 30a，... 30d），用于提高性能并减少缓冲虚拟到绝对地址转换结果所需的芯片面积。 本发明的TLB2组织包括专用于特定CPU的几个小阵列（32a，...，32d），提供与CPU之间共享的主阵列（21）的接口。 专用阵列32a，。 。 。 32d）需要满足架构约束并将多个CPU链接到常用的共享阵列（21）。

公开(公告)号：US08151085B2

公开(公告)日：2012-04-03

申请号：US12353478

申请日：2009-01-14

申请人： Joerg Deutschle ,  Ute Gaertner ,  Erwin Pfeffer ,  Chung-Lung Kevin Shum ,  Bruce Wagar

发明人： Joerg Deutschle ,  Ute Gaertner ,  Erwin Pfeffer ,  Chung-Lung Kevin Shum ,  Bruce Wagar

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/1036 ,  G06F9/45558 ,  G06F12/0888 ,  G06F2009/45583

摘要： The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.

摘要翻译： 本发明涉及一种用于运行多级虚拟机的系统中的地址转换方法，该虚拟机包含分层组织的翻译后备缓冲器，其包括至少两个链接的分层子单元，第一子单元包括用于某些更高级地址转换的后备缓冲器 并且第二子单元包括用于一些较低级别地址转换级别的后备缓冲器，并且所述第二子单元被布置为将上级子单元的TLB索引地址信息作为标签信息存储在其较低级别的TLB结构中 包括以下步骤：在不同的虚拟机级上收集中间的地址转换结果; 并且将中间翻译结果缓冲到翻译后备缓冲器中。

公开(公告)号：US20090187731A1

公开(公告)日：2009-07-23

申请号：US12353478

申请日：2009-01-14

申请人： Joerg Deutschle ,  Ute Gaertner ,  Erwin Pfeffer ,  Chung-Lung Kevin Shum ,  Bruce Wagar

发明人： Joerg Deutschle ,  Ute Gaertner ,  Erwin Pfeffer ,  Chung-Lung Kevin Shum ,  Bruce Wagar

IPC分类号： G06F12/10 ,  G06F9/455

CPC分类号： G06F12/1036 ,  G06F9/45558 ,  G06F12/0888 ,  G06F2009/45583

摘要： The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.

摘要翻译： 本发明涉及一种用于运行多级虚拟机的系统中的地址转换方法，该虚拟机包含分层组织的翻译后备缓冲器，其包括至少两个链接的分层子单元，第一子单元包括用于某些更高级地址转换的后备缓冲器 并且第二子单元包括用于一些较低级别地址转换级别的后备缓冲器，并且所述第二子单元被布置为将上级子单元的TLB索引地址信息作为标签信息存储在其较低级别的TLB结构中 包括以下步骤：在不同的虚拟机级上收集中间的地址转换结果; 并且将中间翻译结果缓冲到翻译后备缓冲器中。

公开(公告)号：US20080320216A1

公开(公告)日：2008-12-25

申请号：US12142885

申请日：2008-06-20

申请人： Matthias Fertig ,  Ute Gaertner ,  Norbert Hagspiel ,  Erwin Pfeffer

发明人： Matthias Fertig ,  Ute Gaertner ,  Norbert Hagspiel ,  Erwin Pfeffer

IPC分类号： G06F12/00

CPC分类号： G06F12/1036

摘要： A program product, a translation lookaside buffer and a related method for operating the TLB is provided. The method comprises the steps of: a) when adding an entry for a virtual address to said TLB testing whether the attribute data of said virtual address is already stored in said CAM and if the attribute data is not stored already in said CAM, generating tag data for said virtual address such that said tag data is different from the tag data generated for the other virtual addresses currently stored in said RAM and associated to the new entry in said CAM for the attribute data, adding the generated tag data to said RAM and to the associated entry in said CAM, and setting a validity flag in said CAM for said associated entry; else if the attribute data is stored already in said CAM, adding the stored attribute data to the entry in said RAM for said virtual address; and when performing a TLB lookup operation: reading the validity flag and the tag data from the entry in said CAM, which is associated to the entry in said RAM for said virtual address, and simultaneously reading the absolute address and the tag data from the entry in said RAM for said virtual address, and generating a TLB hit only if the tag data read from said CAM is valid and matches the tag data read from said RAM.

摘要翻译： 提供了一种程序产品，翻译后备缓冲器和用于操作TLB的相关方法。 该方法包括以下步骤：a）当向所述TLB添加虚拟地址的条目时，测试所述虚拟地址的属性数据是否已经存储在所述CAM中，并且属性数据是否已经存储在所述CAM中，生成标签 用于所述虚拟地址的数据，使得所述标签数据不同于当前存储在所述RAM中并与所述CAM中的新条目相关联的用于属性数据的其他虚拟地址生成的标签数据，将生成的标签数据添加到所述RAM， 到所述CAM中的相关联的条目，并且在所述CAM中为所述相关联的条目设置有效标志; 否则如果属性数据已经存储在所述CAM中，则将存储的属性数据添加到用于所述虚拟地址的所述RAM中的条目; 并且当执行TLB查找操作时：从与所述RAM中的所述虚拟地址的条目相关联的所述CAM中的条目读取有效性标志和标签数据，并同时从所述条目读取绝对地址和标签数据 在所述RAM中用于所述虚拟地址，并且仅当从所述CAM读取的标签数据有效并且与从所述RAM读取的标签数据匹配时才产生TLB命中。

公开(公告)号：US20050055544A1

公开(公告)日：2005-03-10

申请号：US10900537

申请日：2004-07-28

申请人： Ute Gaertner ,  Erwin Pfeffer ,  Charles Webb

发明人： Ute Gaertner ,  Erwin Pfeffer ,  Charles Webb

IPC分类号： G06F9/32 ,  G06F15/00

CPC分类号： G06F9/30054 ,  G06F9/30058

摘要： The present invention relates to a central processing unit comprising: (a) a number of functional units (A, B, . . . , N), (b) at least one module for processing of a function call received from one of the functional units, the module having a decoder to obtain an instruction address from the function call, a memory for storing a plurality of control instructions and for storing a plurality of branch instructions, each control instruction having an assigned instruction address for a next instruction and each branch instruction having assigned at least two alternative instruction addresses for a next instruction, first logic circuitry for processing of the branch instructions in order to select one of the at least two alternative instruction addresses of one of the branch instructions, second logic circuitry for processing of the control instructions in order to return a result in response to the function call.

摘要翻译： 本发明涉及一种中央处理单元，包括：（a）多个功能单元（A，B，...，N），（b）至少一个模块，用于处理从功能性 单元，该模块具有从功能调用获得指令地址的解码器，用于存储多个控制指令并存储多个分支指令的存储器，每个控制指令具有分配的下一个指令的指令地址和每个分支 为下一个指令分配了至少两个备选指令地址的指令，第一逻辑电路，用于处理分支指令以便选择一个分支指令的至少两个备选指令地址之一;第二逻辑电路，用于处理 控制指令，以便响应函数调用返回结果。

公开(公告)号：US06418522B1

公开(公告)日：2002-07-09

申请号：US09501741

申请日：2000-02-11

申请人： Ute Gaertner ,  John MacDougall ,  Erwin Pfeffer ,  Kerstin Schelm

发明人： Ute Gaertner ,  John MacDougall ,  Erwin Pfeffer ,  Kerstin Schelm

IPC分类号： G06F1210

CPC分类号： G06F12/1027 ,  G06F2212/681

摘要： The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB1 and a larger second level TLB2. The second level TLB feeds address information to the first level TLB when the desired virtual address is not contained in the first level TLB. According to the invention the second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one, a higher level unit covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. According to the present invention, some address information holds some number of middle level virtual address (MLVA) bits, i.e., 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit. Thus, the same information is used as a tag information in the lower-level sub-unit and is used herein as a quick reference in any look-up operation in order to find the absolute address of the concerned virtual address. Further, the commonly used status bits, like; e.g., valid bits, are used in both TLB structures, too.

摘要翻译： 由本发明构成的基本思想是提供一种有利地使用两个缓冲器，小的第一级TLB1和较大的第二级TLB2的翻译后备缓冲器（TLB）装置。 当所需的虚拟地址不包含在第一级TLB中时，第二级TLB将地址信息馈送到第一级TLB。 根据本发明，第二级TLB有利地包括两个n路组合关联子单元，其中一个较高级别单元覆盖一些较高级地址转换级别，而另一级单元覆盖一些较低级别的地址转换级别 级别翻译水平。 根据本发明，一些地址信息例如保持一些中间虚拟地址（MLVA）位，即8位，能够用作覆盖上位子单元的地址范围的索引地址。 因此，相同的信息用作下级子单元中的标签信息，并且在本文中用作任何查找操作中的快速参考，以便找到相关虚拟地址的绝对地址。 此外，常用的状态位，如; 例如有效位也用在两个TLB结构中。

公开(公告)号：US5978957A

公开(公告)日：1999-11-02

申请号：US765003

申请日：1997-07-14

申请人： Wilhelm Haller ,  Klaus Getzlaff ,  Erwin Pfeffer ,  Ute Gaertner ,  Gunter Gerwig

发明人： Wilhelm Haller ,  Klaus Getzlaff ,  Erwin Pfeffer ,  Ute Gaertner ,  Gunter Gerwig

IPC分类号： G06F11/10 ,  G06F5/01

CPC分类号： G06F5/015 ,  G06F11/10

摘要： A shifting structure and method which separates a shifting operation into partial shifts which may be executed in different pipeline staged is described herein. In a first pipe stage, an operand is read out and at least one partial shift is accomplished by placing the operand or parts thereof into registers coupled to a shift unit. The shift unit, in a second pipe stage, finalizes the shifting operation executing the remaining partial shifts, thereby reducing the time required for the total shifting operation. A control string is derived in the shift unit based on the shift amount to correct the output of the shifted result as well as providing for parity prediction therefor.

摘要翻译： PCT No.PCT / EP95 / 01456 Sec。 371日期1997年7月14日 102（e）日期1997年7月14日PCT提交1995年4月18日PCT公布。 公开号WO96 / 33455 日期1996年10月24日这里描述了将移动操作分离成可以在不同流水线分段中执行的部分班次的换档结构和方法。 在第一管道级中，读出操作数，并且通过将操作数或其部分放入耦合到移位单元的寄存器来实现至少一个部分移位。 在第二管段中的换档单元完成执行剩余部分换挡的换档操作，从而减少了总换档操作所需的时间。 基于移位量，在移位单元中导出控制串，以校正移位结果的输出以及为此进行奇偶校验。

公开(公告)号：US6108771A

公开(公告)日：2000-08-22

申请号：US15870

申请日：1998-01-29

申请人： Ute Gaertner ,  Klaus Jorg Getzlaff ,  Erwin Pfeffer ,  Hans-Werner Tast

发明人： Ute Gaertner ,  Klaus Jorg Getzlaff ,  Erwin Pfeffer ,  Hans-Werner Tast

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.

摘要翻译： 描述了允许使用最少数量的物理寄存器的无序处理系统中的寄存器重命名和分配的系统和方法。 链接列表允许将表示相应逻辑寄存器的某个实例的物理寄存器连接到表示相同逻辑寄存器的下一个实例的物理寄存器。 通过添加和删除此链接列表中的链接，可以动态地管理物理寄存器到逻辑寄存器的分配。 表示推测实例的物理寄存器和表示顺序实例的物理寄存器都被一起管理。 这是通过一个顺序列表来完成的，它列出了实际表示机器的架构状态的物理寄存器。

公开(公告)号：US5996063A

公开(公告)日：1999-11-30

申请号：US815351

申请日：1997-03-11

申请人： Ute Gaertner ,  Klaus Jorg Getzlaff ,  Thomas Koehler ,  Erwin Pfeffer

发明人： Ute Gaertner ,  Klaus Jorg Getzlaff ,  Thomas Koehler ,  Erwin Pfeffer

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3012 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3863

摘要： The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers.Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state.The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.

摘要翻译： 本发明涉及超标量计算机系统中注册重命名和分配的领域。 当指令流中的多个指令读取或写入某个逻辑寄存器时，所述逻辑寄存器将必须由多个物理寄存器表示。 因此，每个逻辑寄存器必须存在多个物理重命名寄存器。 所述重命名寄存器中最老的一个定义了计算机系统的架构状态，即按顺序状态。 本发明提供了一种用于管理各种寄存器实例的方法。 表示按顺序状态的寄存器和各种重命名实例都保存在一个通用循环缓冲器中。 每个逻辑寄存器存在两个指针：第一个，按顺序指针指向表示按顺序状态的寄存器，第二个是重命名指针，指向最近的重命名实例。