MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE

    公开(公告)号:US20220238436A1

    公开(公告)日:2022-07-28

    申请号:US17342699

    申请日:2021-06-09

    申请人: VIA LABS, INC.

    发明人: Sheng-Yuan LEE

    IPC分类号: H01L23/522 H01F27/28

    摘要: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric (IMD) layer, and first and second winding portions symmetrically arranged in the IMD layer and the insulating redistribution layer with respect to a symmetrical axis. The first and second winding portions each includes at least first and second semi-circular stacking layers arranged from the inside to the outside and in concentricity. The first and second semi-circular stacking layers each has a first trace layer in the insulating redistribution layer and a second trace layer in the IMD layer and correspondingly formed below the first trace layer. A first slit opening passes through the second trace layer and extends in the extending direction of the length of the second trace layer.

    MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE
    2.
    发明公开

    公开(公告)号:US20230187347A1

    公开(公告)日:2023-06-15

    申请号:US18165498

    申请日:2023-02-07

    申请人: VIA LABS, INC.

    发明人: Sheng-Yuan LEE

    IPC分类号: H01L23/522 H01F27/28

    摘要: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer correspondingly formed below the first spiral trace layer, wherein the inter-metal dielectric layer has a separating region to divide the second spiral trace layer into a plurality of line segments, and wherein each of a plurality of first slit openings and each of a plurality of second slit openings pass through a corresponding line segment, and extend in an extending direction of a length of the corresponding line segment.

    ON-CHIP INDUCTOR STRUCTURE
    3.
    发明申请

    公开(公告)号:US20210126085A1

    公开(公告)日:2021-04-29

    申请号:US16741135

    申请日:2020-01-13

    申请人: VIA LABS, INC.

    发明人: Sheng-Yuan LEE

    摘要: An on-chip inductor structure includes first and second winding portions symmetrically arranged in an insulating layer by a symmetrical axis. Each of the first and second winding portions includes first and second semi-circular conductive lines concentrically arranged from the inside to the outside. First and second input/output conductive portions are disposed in the insulating layer along the extending direction of the symmetrical axis, to respectively and electrically couple the first ends of the outermost semi-circular conductive lines. A conductive branch structure is disposed in the insulating layer along the symmetrical axis and between the first and second input/output conductive portions, and electrically coupled to first ends of the innermost semi-circular conductive lines. The conductive branch structure has a grounded first end and a second end is electrically coupled to a circuit and is opposite the first end of the conductive branch structure.

    MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE
    4.
    发明公开

    公开(公告)号:US20230207612A1

    公开(公告)日:2023-06-29

    申请号:US17690580

    申请日:2022-03-09

    申请人: VIA LABS, INC.

    发明人: Sheng-Yuan LEE

    摘要: A multilayer-type on-chip inductor includes a first winding portion arranged in an inter-metal dielectric (IMD) layer, which includes first and second semi-circular stacking layers arranged from inside to outside and in concentricity. A second winding portion includes third and fourth semi-circular stacking layers arranged symmetrically with the first semi-circular stacking layer and the second semi-circular stacking layer, respectively, with respect to a symmetry axis. A conductive branch layer is disposed in an insulating redistribution layer over the IMD layer. The first, second, third, and fourth semi-circular stacking layers each include an uppermost trace layer and a next uppermost trace layer vertically stacked under the uppermost trace layer.

    MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE

    公开(公告)号:US20220238435A1

    公开(公告)日:2022-07-28

    申请号:US17342684

    申请日:2021-06-09

    申请人: VIA LABS, INC.

    发明人: Sheng-Yuan LEE

    IPC分类号: H01L23/522 H01L49/02

    摘要: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first spiral trace layer.
    The inter-metal dielectric layer has a separating region to divide the second spiral trace layer into line segments. First slit openings each passes through a corresponding line segment, and extends in an extending direction of a length of the corresponding line segment.

    MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE
    6.
    发明公开

    公开(公告)号:US20240266283A1

    公开(公告)日:2024-08-08

    申请号:US18185500

    申请日:2023-03-17

    申请人: VIA LABS, INC.

    发明人: Sheng-Yuan LEE

    摘要: A multilayer-type on-chip inductor structure includes an inter-metal dielectric (IMD) layer having an inductor central region, a first metal winding portion disposed in the IMD layer, and a second metal winding portion disposed in the IMD layer and electrically connected to the overlying first metal winding portion. The first metal winding portion includes a first spiral-type coil surrounding the inductor central region and a first open ring-type coil surrounding the first spiral-type coil. The second metal winding portion includes a second spiral-type coil vertically overlapping the first spiral-type coil and the first open ring-type coil, so that the outermost-turn coil of the second spiral-type coil corresponds to the first open ring-type coil.