公开(公告)号：US20220404891A1

公开(公告)日：2022-12-22

申请号：US17895027

申请日：2022-08-24

Applicant: VIA LABS, INC.

Inventor： Tze-Shiang Wang ,  Hui-Neng Chang ,  Nai-Chuan Hung ,  Sheng-Hsien Yen

IPC: G06F1/3234

Abstract: A power management device and a consumer electronic product are provided. The power management device is for the consumer electronic product. The power management device includes a memory and a controller. The memory stores a power information of a load of the consumer electronic product. An input end of the first voltage regulator is coupled to a power pin of an upstream USB connector, and an output end of the first voltage regulator is coupled to a power end of the load. When USB device is connected to a downstream USB connector of the consumer electronic product, the controller obtains a power demand from the USB device, the controller determines whether to change a power mode of the upstream USB connector according to the power information and the power demand, and the controller controls the second voltage regulator according to the power mode to supply power to the USB device.

公开(公告)号：US20220238436A1

公开(公告)日：2022-07-28

申请号：US17342699

申请日：2021-06-09

Applicant: VIA LABS, INC.

Inventor： Sheng-Yuan LEE

IPC: H01L23/522 ,  H01F27/28

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric (IMD) layer, and first and second winding portions symmetrically arranged in the IMD layer and the insulating redistribution layer with respect to a symmetrical axis. The first and second winding portions each includes at least first and second semi-circular stacking layers arranged from the inside to the outside and in concentricity. The first and second semi-circular stacking layers each has a first trace layer in the insulating redistribution layer and a second trace layer in the IMD layer and correspondingly formed below the first trace layer. A first slit opening passes through the second trace layer and extends in the extending direction of the length of the second trace layer.

公开(公告)号：US11386030B2

公开(公告)日：2022-07-12

申请号：US17110301

申请日：2020-12-03

Applicant: VIA LABS, INC.

Inventor： Cheng-Chung Lin ,  Hsiao-Chyi Lin ,  Yi-Shing Lin ,  Chien-Sheng Chen

IPC: G06F13/38 ,  G06F13/42

Abstract: A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is suitable for coupling to a DP connector. In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit. The USB core circuit decodes the USB signal pair and generates DP data. The DP data is transmitted to the DP connector by the DP interface circuit. In a second operation mode, the DP data received by the USB connector is transmitted to the DP connector through the USB interface circuit, the switching circuit and the DP interface circuit.

公开(公告)号：US11367773B2

公开(公告)日：2022-06-21

申请号：US16741135

申请日：2020-01-13

Applicant: VIA LABS, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L49/02 ,  H01F27/28 ,  H01F27/29 ,  H01F27/32

Abstract: An on-chip inductor structure includes first and second winding portions symmetrically arranged in an insulating layer by a symmetrical axis. Each of the first and second winding portions includes first and second semi-circular conductive lines concentrically arranged from the inside to the outside. First and second input/output conductive portions are disposed in the insulating layer along the extending direction of the symmetrical axis, to respectively and electrically couple the first ends of the outermost semi-circular conductive lines. A conductive branch structure is disposed in the insulating layer along the symmetrical axis and between the first and second input/output conductive portions, and electrically coupled to first ends of the innermost semi-circular conductive lines. The conductive branch structure has a grounded first end and a second end is electrically coupled to a circuit and is opposite the first end of the conductive branch structure.

公开(公告)号：US20210305828A1

公开(公告)日：2021-09-30

申请号：US17110312

申请日：2020-12-03

Applicant: VIA LABS, INC.

Inventor： Terrance Shiyang Shih ,  Chin-Sung Hsu ,  Nai-Chuan Hung

IPC: H02J7/00 ,  G06F1/26 ,  G06F1/3234 ,  G06F13/42

Abstract: Power management device and method for a consumer product are provided. The power management device includes a memory, a configuration channel interface circuit and a control circuit. When a power supply device is electrically connected to a connector of the consumer product, the control circuit performs a power delivery protocol conforming to a USB specification on the power supply device through the configuration channel interface circuit and a configuration channel pin of the connector, so as to determine a power mode in which the power supply device supplies power to the consumer product. After the power delivery protocol is performed successfully, based on at least one protocol profile stored in the memory, the control circuit performs a vendor-defined messaging protocol on the power supply device through the configuration channel interface circuit and the configuration channel pin, so as to determine whether to change the power mode.

公开(公告)号：US20210098343A1

公开(公告)日：2021-04-01

申请号：US16858709

申请日：2020-04-27

Applicant: VIA LABS, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L23/485 ,  H01L23/00

Abstract: An integrated circuit chip has an active surface and a chip pad arrangement on the active surface. The chip pad arrangement includes four pairs of chip pads arranged in two rows along a side edge of the active surface. Two pairs of chip pads are a first transmission differential pair chip pad and a first reception differential pair chip pad respectively. Positions of the two pairs of chip pads are not adjacent to each other and are in different rows. The other two pairs of chip pads are a second transmission differential chip pad and a second reception differential chip pad respectively. Positions of the other two pairs of chip pads are not adjacent to each other and are in different rows. In addition, a package substrate corresponding to the integrated circuit chip and an electronic assembly including the package substrate and the integrated circuit chip are also provided.

公开(公告)号：US20200012614A1

公开(公告)日：2020-01-09

申请号：US16503700

申请日：2019-07-05

Applicant: VIA LABS, INC.

Inventor： YU-LUNG LIN ,  HSUAN-JUI CHANG

IPC: G06F13/42 ,  H04L5/16 ,  G06F13/40 ,  H04B3/20

Abstract: For adjusting a signal transmission direction in a cable, which is configured to be electrically coupled between a first interface port and a second interface port, an electric characteristic on at least a first pin of the first interface port is detected. Then a signal transmission direction of at least one pair of differential signal transmission channels in the cable is controlled to change from a first direction to a second direction different from the first direction, provided that a communication protocol between the first interface port and the second interface port is changed from a first communication protocol to a second communication protocol, and the electric characteristic complies with a first condition.

公开(公告)号：US20190235593A1

公开(公告)日：2019-08-01

申请号：US16103941

申请日：2018-08-15

Applicant: VIA Labs, INC.

Inventor： Tze-Shiang Wang ,  Chi-Yuan Kao

IPC: G06F1/26 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F1/266 ,  G06F13/382 ,  G06F13/4282

Abstract: The present invention provides a universal serial bus (USB) device and an operating method thereof. The USB device includes a plurality of Downstream Facing Ports (DFPs) and a control circuit. When a first external device is connected to the first DFP and the second DFP is not connected to any external device, the control circuit maintains the first DFP as one of a power source port and a power sink port according to the first external device, and maintains the second DFP as other one of the power source port and the power sink port regardless of whether the second DFP is connected to a second external device later until the first external device is removed from the first DFP.

公开(公告)号：US11914491B2

公开(公告)日：2024-02-27

申请号：US17985920

申请日：2022-11-14

Applicant: VIA LABS, INC.

Inventor： Hao-Hsuan Chiu

IPC: G06F11/22 ,  G01R1/04 ,  G06F11/273

CPC classification number: G06F11/2273 ,  G01R1/0416 ,  G06F11/221 ,  G06F11/2733 ,  G06F2213/0042

Abstract: A USB integrated circuit (IC), a testing platform and an operating method for USB integrated circuit are provided. The USB integrated circuit includes a USB port physical layer (PHY) circuit, a first lane adapter, a second lane adapter, a routing circuit, and a USB transport layer circuit. The USB PHY circuit is configured to transmit a differential signal between the USB integrated circuit and an outside device. When the USB integrated circuit operates in a testing mode, the routing circuit electrically connects the first lane adapter to the USB PHY circuit. When the USB integrated circuit operates in a working mode, the routing circuit electrically connects the second lane adapter to the USB PHY circuit. The USB transport layer circuit is coupled to the first lane adapter and the second lane adapter.

公开(公告)号：US11735502B2

公开(公告)日：2023-08-22

申请号：US16858709

申请日：2020-04-27

Applicant: VIA LABS, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L23/485 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/485 ,  H01L23/49838 ,  H01L24/06 ,  H01L2224/0615 ,  H01L2224/06515

Abstract: An integrated circuit chip has an active surface and a chip pad arrangement on the active surface. The chip pad arrangement includes four pairs of chip pads arranged in two rows along a side edge of the active surface. Two pairs of chip pads are a first transmission differential pair chip pad and a first reception differential pair chip pad respectively. Positions of the two pairs of chip pads are not adjacent to each other and are in different rows. The other two pairs of chip pads are a second transmission differential chip pad and a second reception differential chip pad respectively. Positions of the other two pairs of chip pads are not adjacent to each other and are in different rows. In addition, a package substrate corresponding to the integrated circuit chip and an electronic assembly including the package substrate and the integrated circuit chip are also provided.