公开(公告)号：US09519541B2

公开(公告)日：2016-12-13

申请号：US14271813

申请日：2014-05-07

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Lei Feng

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/108 ,  G06F11/1048 ,  G06F2211/109

Abstract: Data checking and correction for a volatile memory of a data storage device, the data storage device further including a non-volatile memory and a controller. The controller operates the non-volatile memory in accordance with requests issued from a host. The controller uses the volatile memory for temporary storage of temporary data required for operations of the non-volatile memory. The controller generates error checking and correction content for the temporary data and writes the temporary data and the error checking and correction content into the volatile memory in at least one burst length for temporary storage of the temporary data. In this manner, it is not necessary to manufacture any additional pin on the volatile memory for data checking and correction.

Abstract translation: 用于数据存储设备的易失性存储器的数据检查和校正，所述数据存储设备还包括非易失性存储器和控制器。 控制器根据从主机发出的请求来操作非易失性存储器。 控制器使用易失性存储器临时存储非易失性存储器操作所需的临时数据。 控制器产生用于临时数据的错误检查和校正内容，并将临时数据和错误检查和校正内容以至少一个突发长度写入易失性存储器，以临时存储临时数据。 以这种方式，不需要在易失性存储器上制造任何额外的引脚用于数据检查和校正。

公开(公告)号：US09582670B2

公开(公告)日：2017-02-28

申请号：US14463991

申请日：2014-08-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Lei Feng

IPC: G06F21/60 ,  G06F21/79 ,  G06F21/85

CPC classification number: G06F21/602 ,  G06F21/79 ,  G06F21/85

Abstract: A data scrambling and descrambling technology based on logical addresses. A data storage device with the data scrambling and descrambling technology includes a non-volatile memory and a controller. The controller generates a data scrambling seed according to a logical writing address issued from the host, scrambles the write data issued from the host with the data scrambling seed and then stores the scrambled write data into the non-volatile memory. The controller further generates a data descrambling seed according to a logical reading address issued from the host, and descrambles the read data retrieved from the non-volatile memory by the data descrambling seed. The controller further processes the descrambled read data for data checking and correction.

Abstract translation: 基于逻辑地址的数据加扰和解扰技术。 具有数据加扰和解扰技术的数据存储设备包括非易失性存储器和控制器。 控制器根据从主机发出的逻辑写入地址生成数据加扰种子，用数据加扰种子对从主机发出的写入数据进行加扰，然后将加扰的写入数据存储到非易失性存储器中。 控制器还根据从主机发出的逻辑读取地址生成数据解扰种子，并通过数据解扰种子解扰从非易失性存储器检索的读取数据。 控制器进一步处理解扰的读取数据用于数据检查和校正。