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    METHOD FOR SIGNING AND VERIFYING DATA USING MULTIPLE HASH ALGORITHMS AND DIGESTS IN PKCS
    1.
    发明申请
    METHOD FOR SIGNING AND VERIFYING DATA USING MULTIPLE HASH ALGORITHMS AND DIGESTS IN PKCS 有权
    使用PKCS中的多个哈希算法和数据签名和验证数据的方法

    公开(公告)号：US20140019764A1

    公开(公告)日：2014-01-16

    申请号：US13712401

    申请日：2012-12-12

    申请人： VINODH GOPAL ,  SEAN M. GULLEY ,  JAMES D. GUILFORD ,  WAJDI K. FEGHALI

    发明人： VINODH GOPAL ,  SEAN M. GULLEY ,  JAMES D. GUILFORD ,  WAJDI K. FEGHALI

    IPC分类号： H04L9/32

    CPC分类号： H04L9/3247

    摘要： Methods, systems, and apparatuses are disclosed for signing and verifying data using multiple hash algorithms and digests in PKCS including, for example, retrieving, at the originating computing device, a message for signing at the originating computing device to yield a signature for the message; identifying multiple hashing algorithms to be supported by the signature; for each of the multiple hashing algorithms identified to be supported by the signature, hashing the message to yield multiple hashes of the message corresponding to the multiple hashing algorithms identified; constructing a single digest having therein each of the multiple hashes of the messages corresponding to the multiple hashing algorithms identified and further specifying the multiple hashing algorithms to be supported by the signature; applying a signing algorithm to the single digest using a private key of the originating computing device to yield the signature for the message; and distributing the message and the signature to receiving computing devices. Other related embodiments are disclosed.

    摘要翻译： 公开了用于使用PKCS中的多个散列算法和摘要来签名和验证数据的方法，系统和装置，包括例如在起始计算设备处检索用于在始发计算设备处签名的消息以产生该消息的签名 ; 识别签名支持的多个散列算法; 对于被标识为被签名支持的多个散列算法中的每一个，散列消息以产生与识别的多个散列算法相对应的消息的多个哈希; 构建其中具有与识别的多个散列算法相对应的消息的多个散列中的每一个的单个摘要，并进一步指定要由签名支持的多个散列算法; 使用始发计算设备的私钥将签名算法应用于单个摘要以产生该消息的签名; 并将消息和签名分发给接收计算设备。 公开了其他相关实施例。

    TECHNIQUES TO ACCELERATE LOSSLESS COMPRESSION
    2.
    发明申请
    TECHNIQUES TO ACCELERATE LOSSLESS COMPRESSION 审中-公开
    加快无损压缩的技术

    公开(公告)号：US20140006536A1

    公开(公告)日：2014-01-02

    申请号：US13538826

    申请日：2012-06-29

    申请人： JAMES D. GUILFORD ,  VINODH GOPAL ,  GILBERT M. WOLRICH ,  ERDINC OZTURK ,  WAJDI K. FEGHALI

    发明人： JAMES D. GUILFORD ,  VINODH GOPAL ,  GILBERT M. WOLRICH ,  ERDINC OZTURK ,  WAJDI K. FEGHALI

    IPC分类号： G06F15/16 ,  G06F15/167

    CPC分类号： H03M7/60 ,  G06F9/30029 ,  H03M7/3068 ,  H03M7/6058

    摘要： An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a data structure at least one position of at least one subset of characters that are to be encoded as a symbol, (b) comparing, at least in part, at least one pair of multi-byte data words that are of identical predetermined fixed size, (c) maintaining, at least in part, an array of pointers to potentially matching strings that are to be compared with at least one currently examined string, and/or (d) allocating, at least in part, a first buffer portion to store at least one portion of uncompressed data from an application buffer that is to be input for compression to produce a compressed data stream. Other embodiments are described and claimed.

    摘要翻译： 实施例可以包括可以执行压缩相关操作的电路，其可以包括：（a）至少部分地在数据结构中指示要被编码为的至少一个字符子集的至少一个位置 （b）至少部分比较至少一对具有相同预定固定大小的多字节数据字，（c）至少部分维持指向潜在匹配字符串的指针数组， 与至少一个当前检查的字符串进行比较，和/或（d）至少部分地分配第一缓冲器部分，以将来自要输入的压缩数据的至少一部分未压缩数据存储到要压缩的应用缓冲器中 产生压缩数据流。 描述和要求保护其他实施例。

    HYBRID CAM ASSISTED DEFLATE DECOMPRESSION ACCELERATOR
    5.
    发明申请
    HYBRID CAM ASSISTED DEFLATE DECOMPRESSION ACCELERATOR 有权
    混合辅助辅助解码加速器

    公开(公告)号：US20150381202A1

    公开(公告)日：2015-12-31

    申请号：US14317698

    申请日：2014-06-27

    申请人： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  VINODH GOPAL ,  RAM K. KRISHNAMURTHY

    发明人： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  VINODH GOPAL ,  RAM K. KRISHNAMURTHY

    IPC分类号： H03M7/42 ,  G06F12/06

    CPC分类号： G06F12/0646 ,  G06F2212/1021 ,  G06F2212/401 ,  G11C15/00 ,  G11C15/04 ,  H03M7/3059 ,  H03M7/3084 ,  H03M7/3086 ,  H03M7/40

    摘要： Disclosed is an integrated circuit including a memory device including a first portion and a second portion. The first portion is a first type of content addressable memory (CAM) with a first set of cells and the second portion is a second type of CAM with a second set of cells. The first set of cells is smaller than the second set of cells. The integrated circuit further includes a decompression accelerator coupled to the memory device, the decompression accelerator to generate a plurality of length codes. Each of the plurality of length codes include at least one bit. The plurality of length codes are generated using a symbol received from an encoded data stream that includes a plurality of symbols. The decompression accelerator further to store the plurality of length codes in the first portion of the memory device in an order according to their respective number of bits.

    摘要翻译： 公开了一种集成电路，其包括包括第一部分和第二部分的存储器件。 第一部分是具有第一组单元的第一类型的内容可寻址存储器（CAM），并且第二部分是具有第二组单元格的第二类型的CAM。 第一组单元格小于第二组单元格。 集成电路还包括耦合到存储器件的解压加速器，解压加速器以产生多个长度代码。 多个长度码中的每一个包括至少一个位。 使用从包括多个符号的编码数据流接收的符号来生成多个长度码。 所述解压缩加速器进一步按照它们各自的位数按顺序将所述多个长度代码存储在所述存储器件的第一部分中。

    FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION
    8.
    发明申请
    FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION 有权
    用于网络入侵和病毒检测的过滤器

    公开(公告)号：US20100169401A1

    公开(公告)日：2010-07-01

    申请号：US12346734

    申请日：2008-12-30

    申请人： VINODH GOPAL ,  Christopher F. Clark ,  Gilbert Wolrich ,  Wajdi Feghali

    发明人： VINODH GOPAL ,  Christopher F. Clark ,  Gilbert Wolrich ,  Wajdi Feghali

    IPC分类号： G06F17/10

    CPC分类号： H04L63/145 ,  G06F7/02 ,  G06F17/30949 ,  G06F17/30985 ,  G06F21/567 ,  G06F2207/025 ,  H04L63/0245 ,  H04L63/1416

    摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

    摘要翻译： 公开了对网络包检测进行字符串匹配的方法和装置。 在一些实施例中，存在一组字符串匹配限幅电路，该组的每个片电路被配置为与其他片电路并行地执行字符串匹配步骤。 每个切片电路可以包括从输入数据蒸汽存储一些数量的数据字节的输入窗口。 如果需要，可以填充数据的输入窗口，然后乘以多项式模数不可约伽罗瓦域多项式以生成散列索引。 可以访问与散列索引相对应的存储器的存储位置，以产生一组H个切片命中信号的切片命中信号。 切片命中信号可以被提供给AND逻辑阵列，其中H组切片命中信号的组合被逻辑地组合成匹配​​结果。

    HARDWARE ACCELERATORS AND METHODS FOR HIGH-PERFORMANCE AUTHENTICATED ENCRYPTION
    9.
    发明申请
    HARDWARE ACCELERATORS AND METHODS FOR HIGH-PERFORMANCE AUTHENTICATED ENCRYPTION 审中-公开

    公开(公告)号：US20190042249A1

    公开(公告)日：2019-02-07

    申请号：US15943654

    申请日：2018-04-02

    申请人： VIKRAM SURESH ,  SANU MATHEW ,  SUDHIR SATPATHY ,  VINODH GOPAL

    发明人： VIKRAM SURESH ,  SANU MATHEW ,  SUDHIR SATPATHY ,  VINODH GOPAL

    IPC分类号： G06F9/30 ,  G06F9/38 ,  H04L9/06

    摘要： Methods and apparatuses relating to high-performance authenticated encryption are described. A hardware accelerator may include a vector register to store an input vector of a round of an encryption operation; a circuit including a first data path including a first modular adder coupled to a first input from the vector register and a second input from the vector register, and a second modular adder coupled to the first modular adder and a second data path from the vector register, and the second data path including a first logical XOR circuit coupled to the second input and a third data path from the vector register, a first rotate circuit coupled to the first logical XOR circuit, a second logical XOR circuit coupled to the first rotate circuit and the third data path, and a second rotate circuit coupled to the second logical XOR circuit; and a control circuit to cause the first modular adder and the second modular adder of the first data path and the first logical XOR circuit, the second logical XOR circuit, the first rotate circuit, and the second rotate circuit of the second data path to perform a portion of the round according to one or more control values, and store a first result from the first data path for the portion and a second result from the second data path for the portion into the vector register.

    HARDWARE ENFORCED ONE-WAY CRYPTOGRAPHY
    10.
    发明申请
    HARDWARE ENFORCED ONE-WAY CRYPTOGRAPHY 审中-公开

    公开(公告)号：US20170093567A1

    公开(公告)日：2017-03-30

    申请号：US14868579

    申请日：2015-09-29

    申请人： VINODH GOPAL ,  JASON W. BRANDT

    发明人： VINODH GOPAL ,  JASON W. BRANDT

    IPC分类号： H04L9/08 ,  H04L9/32

    CPC分类号： H04L9/0861 ,  G06F21/00 ,  G06F21/602 ,  H04L9/0643 ,  H04L9/3236 ,  H04L9/3239 ,  H04L9/3242 ,  H04L2209/12

    摘要： Embodiments of an invention for hardware enforced one-way cryptography are disclosed. In one embodiment, a processor includes a processor key location, instruction hardware, and execution hardware. The processor key location is to hold a processor key. The instruction hardware is to receive a first instruction in an instruction set of the processor. The first instruction is to encrypt input data with the processor key and return a handle. The instruction set lacks a second instruction corresponding to the first instruction to decrypt the handle with the processor key to return the input data. The execution hardware is to perform, in response to receipt of the first instruction by the instruction hardware, encryption of the input data with the processor key and to return the handle.