公开(公告)号：US20170168948A1

公开(公告)日：2017-06-15

申请号：US14969768

申请日：2015-12-15

Applicant: VMware, Inc.

Inventor： Jorge Guerra DELGADO ,  Wenguang WANG

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0864 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0871 ,  G06F12/0893 ,  G06F2212/1016 ,  G06F2212/222 ,  G06F2212/601

Abstract: A cache is sized using an ordered data structure having data elements that represent different target locations of input-output operations (IOs), and are sorted according to an access recency parameter. The cache sizing method includes continually updating the ordered data structure to arrange the data elements in the order of the access recency parameter as new IOs are issued, and setting a size of the cache based on the access recency parameters of the data elements in the ordered data structure. The ordered data structure includes a plurality of ranked ring buffers, each having a pointer that indicates a start position of the ring buffer. The updating of the ordered data structure in response to a new IO includes updating one position in at least one ring buffer and at least one pointer.