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19 条记录 (耗时 0.024 秒)

    System for closed loop power control using a linear or a non-linear power amplifier
    3.
    发明授权
    System for closed loop power control using a linear or a non-linear power amplifier 有权
    使用线性或非线性功率放大器进行闭环功率控制的系统

    公开(公告)号：US06670849B1

    公开(公告)日：2003-12-30

    申请号：US09650987

    申请日：2000-08-30

    申请人： Morten Damgaard ,  Dmitriy Rozenblit ,  William J. Domino ,  Ricke W. Clark

    发明人： Morten Damgaard ,  Dmitriy Rozenblit ,  William J. Domino ,  Ricke W. Clark

    IPC分类号： H03G320

    CPC分类号： H03G3/3042 ,  H03F1/02 ,  H03F2200/294 ,  H03F2200/372 ,  H04W52/52

    摘要： A system for a closed power control feedback loop allows for the use of a non-linear amplifier for amplifying a phase modulated (PM) signal while introducing an inverse version of the desired amplitude modulated (AM) signal into the feedback loop using a variable gain element. By introducing an inverse version of the desired AM portion of the signal into the power control feedback loop, the non-linear, and highly efficient, power amplifier may be used to amplify only the PM portion of the signal, while the AM portion is introduced by the power control feedback loop. In another aspect of the invention, an inverse version of the AM portion of the desired transmit signal is introduced into the power control feedback loop of an amplifier that is amplifying both a phase modulated signal and an amplitude modulated signal. By introducing an inverse version of the desired AM signal into the power control feedback loop, the power control feedback loop may not cancel the AM component present at the output of the power amplifier. In yet another aspect of the invention, the desired AM signal is injected into the feedback loop along with the power control reference signal.

    摘要翻译： 用于闭合功率控制反馈回路的系统允许使用非线性放大器来放大相位调制（PM）信号，同时使用可变增益将所需幅度调制（AM）信号的逆版本引入反馈环路 元件。 通过将信号的期望的AM部分的逆版本引入功率控制反馈回路中，可以使用非线性和高效的功率放大器来仅放大信号的PM部分，同时引入AM部分 通过功率控制反馈回路。 在本发明的另一方面，将期望的发送信号的AM部分的逆版本引入放大器的功率控制反馈环路，该放大器正在放大相位调制信号和幅度调制信号。 通过将所需AM信号的逆版本引入功率控制反馈回路中，功率控制反馈回路可能不会消除存在于功率放大器输出端的AM分量。 在本发明的另一方面，所需的AM信号与功率控制参考信号一起被注入到反馈回路中。

    Method of estimating carrier frequency in a digital mobile communications system through multiple hypotheses performed on the received signal
    4.
    发明授权
    Method of estimating carrier frequency in a digital mobile communications system through multiple hypotheses performed on the received signal 有权
    通过对接收到的信号执行的多个假设来估计数字移动通信系统中载波频率的方法

    公开(公告)号：US06459888B1

    公开(公告)日：2002-10-01

    申请号：US09164534

    申请日：1998-09-30

    申请人： Ricke W. Clark

    发明人： Ricke W. Clark

    IPC分类号： H04B106

    CPC分类号： H04L27/22 ,  H04L2027/0034

    摘要： A multiple-hypothesis frequency detection or demodulation system and method in a mobile communication system such as a GSM mobile telephone system includes a GSM mobile unit for demodulating the received signal by applying three hypotheses. The first hypothesis is based on the assumption that transmitted signal was received without frequency offset or phase rotation. The second hypothesis assumes a phase rotation of +a degrees on the first half of a burst and a phase rotation of −a degrees on the following half burst. Finally, the third hypothesis assumes that the data burst has a phase rotation of −a degrees on the first half burst and a phase rotation of +a degrees on the next following half burst. Any frequency offset is estimated based on a comparison of the results of the three separate demodulation attempts. Based on the frequency offset estimate, the transmitted signal may be demodulated without adjustment of the local oscillator.

    摘要翻译： 在诸如GSM移动电话系统的移动通信系统中的多重假设频率检测或解调系统和方法包括通过应用三个假设来解调接收信号的GSM移动单元。 第一个假设是基于传输信号没有频率偏移或相位旋转的假设。 第二个假设假定在脉冲串的前半部分为+ a度的相位旋转，在下一个半脉冲串上为-a度的相位旋转。 最后，第三假设假设数据脉冲串在第一个半脉冲串上具有-a度的相位旋转，并且在下一个半脉冲串上具有+ a度的相位旋转。 基于三个独立解调尝试的结果的比较来估计任何频率偏移。 基于频率偏移估计，可以在不调整本地振荡器的情况下解调所发送的信号。

    Triple register RISC digital signal processor
    6.
    发明授权
    Triple register RISC digital signal processor 失效
    三路寄存器RISC数字信号处理器

    公开(公告)号：US5586284A

    公开(公告)日：1996-12-17

    申请号：US547050

    申请日：1995-10-23

    申请人： Keith M. Bindloss ,  Ricke W. Clark ,  Kenneth E. Garey ,  George A. Watson ,  Lawrence F. Blank

    发明人： Keith M. Bindloss ,  Ricke W. Clark ,  Kenneth E. Garey ,  George A. Watson ,  Lawrence F. Blank

    IPC分类号： G06F9/34 ,  G06F9/355 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/00

    CPC分类号： G06F9/355

    摘要： The STREAMER FOR RISC DIGITAL SIGNAL PROCESSOR shown herein allows a CPU 46 to interface with a memory 60 via data registers 50. Pre-fetch and post-store of the correct address is determined by an address generator 58 according to a rule determined by a context register 52. An index indicative of this address is stored in an index register 54. The data, context, and index registers together form a streamer 56, streaming data between the CPU 46 and data memory 60. The rule of the context register 52 also drives a converter 62 for converting data between memory format and register format. The speed and flexibility of a RISC device is combined with the intensive memory access of a digital signal processor.

    摘要翻译： 本文所示的用于RISC数字信号处理器的流程允许CPU 46经由数据寄存器50与存储器60接口。正确地址的预取和后存储由地址生成器58根据由上下文确定的规则来确定 指示该地址的索引被存储在索引寄存器54中。数据，上下文和索引寄存器一起形成流分送器56，在CPU 46和数据存储器60之间流传输数据。上下文寄存器52的规则也 驱动用于在存储器格式和寄存器格式之间转换数据的转换器62。 RISC设备的速度和灵活性与数字信号处理器的密集存储器访问相结合。

    Using a low frequency timer to restore timing to a high frequency timer
    7.
    发明授权
    Using a low frequency timer to restore timing to a high frequency timer 有权
    使用低频定时器将定时恢复到高频定时器

    公开(公告)号：US07236810B1

    公开(公告)日：2007-06-26

    申请号：US09164432

    申请日：1998-09-30

    申请人： Paul A. Underbrink ,  Michael D. Tomlinson ,  Ricke W. Clark

    发明人： Paul A. Underbrink ,  Michael D. Tomlinson ,  Ricke W. Clark

    IPC分类号： H04B1/38 ,  H04M1/00

    CPC分类号： H04W52/029 ,  Y02D70/122 ,  Y02D70/164

    摘要： A low frequency timing circuit is used to reestablish a timing signal in a high-frequency timing circuit after the high frequency timing circuit has lost and regained power. The timing of the low frequency circuit is measured against the timing of the high frequency circuit before the high frequency circuit has lost power. The low frequency circuit then is used to measure time after the high frequency circuit has lost power. Once the high frequency circuit has regained power, its timing signal is reestablished at an appropriate time based on a time measurement obtained from the low frequency circuit.

    摘要翻译： 低频定时电路用于在高频定时电路丢失并恢复供电之后重新建立高频定时电路中的定时信号。 在高频电路断电之前，针对高频电路的定时测量低频电路的定时。 然后，低频电路用于在高频电路断电后测量时间。 一旦高频电路恢复供电，其定时信号就会根据从低频电路获得的时间测量值在适当的时间重新建立。

    System for synchronizing a portable transceiver to a network
    8.
    发明授权
    System for synchronizing a portable transceiver to a network 有权
    用于将便携式收发器同步到网络的系统

    公开(公告)号：US07155176B2

    公开(公告)日：2006-12-26

    申请号：US10820252

    申请日：2004-04-08

    申请人： Jaleh Komaili ,  Darioush Agahi ,  Ricke W. Clark

    发明人： Jaleh Komaili ,  Darioush Agahi ,  Ricke W. Clark

    IPC分类号： H04B1/40

    CPC分类号： H04B7/2662 ,  H04B7/2675 ,  H04L27/2332 ,  H04L2027/0065 ,  H04W56/0035

    摘要： A system for synchronizing a portable transceiver to a network is disclosed. Embodiments of the system for synchronizing a portable transceiver to a network include a crystal oscillator, a frequency synthesizer adapted to receive an output of the crystal oscillator, logic coupled to the crystal oscillator, the logic configured to estimate a frequency error of a received signal; and a first control signal supplied from the logic to the frequency synthesizer, the first control signal configured to adjust the frequency synthesizer to compensate for the error.

    摘要翻译： 公开了一种用于将便携式收发器同步到网络的系统。 用于将便携式收发器同步到网络的系统的实施例包括晶体振荡器，适于接收晶体振荡器的输出的频率合成器，耦合到晶体振荡器的逻辑，被配置为估计接收信号的频率误差的逻辑; 以及从逻辑提供给频率合成器的第一控制信号，第一控制信号被配置为调整频率合成器以补偿误差。

    Method and apparatus for producing a modulated signal
    9.
    发明授权
    Method and apparatus for producing a modulated signal 有权
    用于产生调制信号的方法和装置

    公开(公告)号：US06754287B2

    公开(公告)日：2004-06-22

    申请号：US09814196

    申请日：2001-03-21

    申请人： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

    发明人： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

    IPC分类号： H04L2720

    CPC分类号： H03F3/217 ,  H03F2200/331 ,  H04L27/2046

    摘要： Communications systems, and particularly portable personal communications systems, such as portable phones, are becoming increasingly digital. One area that has remained largely analog, however, is the modulation and RF amplifier circuits. To produce a RF frequency waveform. An output of a class D amplifier is coupled to an integrator to create an analog signal. A resonant circuit shapes an output waveform based on the analog signal to create a sinusoidal RF broadcast signal. The waveform of the class D amplifier may be duty cycle modulated. Digital modulation may occur using a digital sigma delta modulator or a digital programmable divide modulator. Using the digital modulation techniques and class D amplification techniques together allows for broadcast a PSK signal that has been decomposed into amplitude and phase components.

    摘要翻译： 通信系统，特别是诸如便携式电话的便携式个人通信系统正在变得越来越数字化。 然而，仍然是模拟的一个领域是调制和RF放大器电路。 产生RF频率波形。 D类放大器的输出耦合到积分器以产生模拟信号。 谐振电路基于模拟信号对输出波形进行整形以产生正弦RF广播信号。 D类放大器的波形可以是占空比调制的。 可以使用数字Σ-Δ调制器或数字可编程分频调制器进行数字调制。 一起使用数字调制技术和D类放大技术可以广播已经分解为幅度和相位分量的PSK信号。

    Critical path adaptive power control
    10.
    发明授权
    Critical path adaptive power control 有权

    公开(公告)号：US06535735B2

    公开(公告)日：2003-03-18

    申请号：US09814921

    申请日：2001-03-22

    申请人： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

    发明人： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

    IPC分类号： H04Q720

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： Modern digital integrated circuits are commonly synchronized in their workings by clock circuits. The clock frequency for a circuit must take into account the propagation delay of signals within the critical path of the circuit. If the clock time is not adequate to allow propagation of signals through the critical path, improper circuit operation may result. The propagation delay is not a constant from circuit to circuit, and even in a single circuit may change due to temperature, power supply voltage and the like. Commonly, this variation is handled by assuming a worse case propagation delay of the critical path, and then designing the clock frequency and minimum power supply voltage of the circuit so that the circuit will function under worst case conditions. However, instead of assuming a worse case propagation delay of the critical path, the propagation delay may be measured in an actual circuit path that has been constructed to be the equivalent to, or slightly worse than, the propagation delay of the critical path. By knowing the actual worst case propagation delay, the circuit may be modified to operate with lower power supply voltages, conserving power and/or to controlling the frequency of the clock, so that the clock may be operated at or near the circuit's actual, not theoretical worst case limit. Such modifications of power supply voltage and/or clock frequency may occur during circuit operation and thus, adapt the circuit to the different operating parameters of each circuit.