公开(公告)号：US08723256B1

公开(公告)日：2014-05-13

申请号：US13670951

申请日：2012-11-07

Applicant: Vanguard International Semiconductor Corporation

Inventor： Wen-Cheng Lin ,  Shang-Hui Tu ,  Shin-Cheng Lin

IPC: H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0634 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device is provided. The device includes a semiconductor substrate and a gate structure thereon. A well region is formed in the semiconductor substrate. A drain region and a source region are respectively formed in the semiconductor substrate inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. The semiconductor substrate and the first heavily doped region have a first conductivity type and the well region and the second heavily doped region have a second conductivity type. A method for fabricating a semiconductor device is also disclosed.

Abstract translation: 提供半导体器件。 该器件包括半导体衬底及其上的栅极结构。 在半导体衬底中形成阱区。 漏极区域和源极区域分别形成在阱区域内部和外部的半导体衬底中。 在漏极区域和源极区域之间的阱区域中形成至少一组第一和第二重掺杂区域，其中第一和第二重掺杂区域从底部到顶部垂直堆叠并且具有较大的掺杂浓度 而不是井区。 半导体衬底和第一重掺杂区域具有第一导电类型，阱区和第二重掺杂区具有第二导电类型。 还公开了一种制造半导体器件的方法。

公开(公告)号：US08704300B1

公开(公告)日：2014-04-22

申请号：US13670818

申请日：2012-11-07

Applicant: Vanguard International Semiconductor Corporation

Inventor： Wen-Cheng Lin ,  Shang-Hui Tu ,  Shin-Cheng Lin

IPC: H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0634 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed thereon is disclosed. A well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate. A drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions of the first and second conductivity type, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. A gate structure is disposed on the epitaxial structure. A method for fabricating a semiconductor device is also disclosed.

Abstract translation: 公开了一种包括第一导电类型的半导体衬底和设置在其上的第一导电类型的外延结构的半导体器件。 在外延结构和半导体衬底中形成第二导电类型的阱区。 漏极区域和源极区域分别形成在阱区域内部和外部的外延结构中。 至少一组第一和第二重掺杂区域形成在漏极区域和源极区域之间的阱区域中，其中第一和第二导电类型的第一和第二重掺杂区域分别从底部垂直堆叠 并且具有比井区域更大的掺杂浓度。 栅极结构设置在外延结构上。 还公开了一种制造半导体器件的方法。