-
公开(公告)号：US11955397B2
公开(公告)日：2024-04-09
申请号：US17092851
申请日：2020-11-09
Inventor： Shin-Cheng Lin , Cheng-Wei Chou , Ting-En Hsieh , Yi-Han Huang , Kwang-Ming Lin , Yung-Fong Lin , Cheng-Tao Chou , Chi-Fu Lee , Chia-Lin Chen , Shu-Wen Chang
IPC: H01L29/778 , H01L23/31 , H01L29/66 , H01L21/02 , H01L23/29 , H01L29/20 , H01L29/205
CPC classification number: H01L23/3192 , H01L23/3171 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L21/0206 , H01L23/291 , H01L29/2003 , H01L29/205
Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
-
公开(公告)号：US11876118B2
公开(公告)日：2024-01-16
申请号：US16791010
申请日：2020-02-14
Inventor： Shin-Cheng Lin , Cheng-Wei Chou
IPC: H01L29/423 , H01L29/778 , H01L29/417 , H01L29/40
CPC classification number: H01L29/42376 , H01L29/402 , H01L29/41775 , H01L29/7786
Abstract: A semiconductor structure includes a substrate, a gate structure on the substrate, and a source structure and a drain structure on opposite sides of the gate structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. The gate metal layer has at least one notch, which exposes the gate electrode below. The electric potential of the source structure is different from that of the gate structure.
-
公开(公告)号：US10424659B1
公开(公告)日：2019-09-24
申请号：US15973888
申请日：2018-05-08
Inventor： Shin-Cheng Lin , Hsin-Chih Lin , Yung-Hao Lin , Chia-Ching Huang
IPC: H01L29/778 , H01L29/06 , H01L29/10
Abstract: A high electron mobility transistor includes a buffer layer, a threshold voltage adjustment layer, a band adjustment layer, a first enhancement layer, a gate electrode, and source/drain electrodes. The threshold voltage adjustment layer is disposed on the buffer layer. A channel region is disposed in the buffer layer adjacent to an interface between the buffer layer and the threshold voltage adjustment layer. The band adjustment layer is disposed on the threshold voltage adjustment layer. The first enhancement layer is conformally covering the threshold voltage adjustment layer and the band adjustment layer. The gate electrode is disposed on the first enhancement layer. The source/drain electrodes are disposed on the buffer layer through the threshold voltage adjustment layer and the first enhancement layer on opposite sides of the gate electrode respectively. The threshold voltage adjustment layer and the first enhancement layer are III-V semiconductors.
-
公开(公告)号：US10033260B2
公开(公告)日：2018-07-24
申请号：US14957163
申请日：2015-12-02
Inventor： Yu-Lung Chin , Shin-Cheng Lin , Wen-Hsin Lin , Yu-Hao Ho
Abstract: A switch-mode converter includes a high-side driver, a high-side transistor, a low-side driver, a low-side transistor, a capacitor, and an active diode. The high-side driver is supplied by the bootstrap voltage of the bootstrap node and a floating reference voltage of a floating reference node, and generates the high-side output signal. The high-side transistor provides an input voltage to the floating reference node according to the high-side output signal. The low-side driver generates the low-side output signal. The low-side transistor couples the floating reference node to a ground according to the low-side output signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides the supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node.
-
公开(公告)号：US10032938B1
公开(公告)日：2018-07-24
申请号：US15723802
申请日：2017-10-03
Inventor： Chien-Wei Chiu , Shin-Cheng Lin , Yung-Hao Lin
IPC: H01L21/00 , H01L29/872 , H01L29/20 , H01L21/322 , H01L21/265 , H01L21/02 , H01L29/66
Abstract: A semiconductor device includes a first gallium nitride layer disposed on a semiconductor substrate, wherein the first gallium nitride layer has a first conductivity type. The semiconductor device also includes a second gallium nitride layer disposed on the first gallium nitride layer, wherein the second gallium nitride layer has the first conductivity type, and the first gallium nitride layer has a dopant concentration which is greater than that of the second gallium nitride layer. The semiconductor device further includes an anode electrode disposed on the second gallium nitride layer, a cathode electrode disposed on and in direct contact with the first gallium nitride layer, and an insulating region disposed on and in direct contact with the first gallium nitride layer, wherein the insulating region is located between the cathode electrode and the second gallium nitride layer.
-
Patent Agency Ranking
公开(公告)号：US10014408B1
公开(公告)日：2018-07-03
申请号：US15608514
申请日：2017-05-30
Inventor： Shin-Cheng Lin , Yu-Hao Ho , Wen-Hsin Lin , Cheng-Tsung Wu , Manoj Kumar
CPC classification number: H01L29/7817 , H01L29/0634 , H01L29/0653 , H01L29/1083 , H01L29/42368 , H01L29/66681 , H01L29/7835
Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, and a first well region disposed in the semiconductor substrate, wherein the first well region has a second conductivity type opposite to the first conductivity type. The semiconductor device also includes a buried layer disposed in the semiconductor substrate and under the first well region, wherein the buried layer has the first conductivity type and is in contact with the first well region. The semiconductor device further includes a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode.
-
公开(公告)号：US09842896B1
公开(公告)日：2017-12-12
申请号：US15436158
申请日：2017-02-17
Inventor： Yu-Hao Ho , Wen-Hsin Lin , Shin-Cheng Lin
IPC: H01L29/66 , H01L29/06 , H01L29/40 , H01L21/265
CPC classification number: H01L29/0634 , H01L21/26513 , H01L29/408
Abstract: An ultra-high voltage device is provided. The ultra-high voltage device includes a substrate, a first well zone formed in the substrate, a second well zone formed in the substrate adjacent to the first well zone, a gate oxide layer formed on the first well zone and the second well zone, a gate formed on the gate oxide layer, an insulation region formed on the surface of the second well zone, a first implant region formed in the second well zone underneath the insulation region, a second implant region formed below the first implant region, and a junction formed between the first implant region and the second implant region. At least one of the first implant region and the second implant region includes at least two sub-implant regions having different implant concentrations. The sub-implant region having the higher implant concentration is adjacent to the junction.
-
公开(公告)号：US09577506B1
公开(公告)日：2017-02-21
申请号：US14981226
申请日：2015-12-28
Inventor： Yu-Lung Chin , Shin-Cheng Lin , Wen-Hsin Lin , Yu-Hao Ho
CPC classification number: H02M1/088 , H02M1/08 , H02M2001/0003 , H03K17/063 , H03K2217/0063 , H03K2217/0072 , H03K2217/0081
Abstract: A high-side circuit, adapted for a switched-mode converter, includes a level shifter, a high-side driver, a high-side transistor, a capacitor, and an active diode. The level shifter receives a first signal to generate a set signal. The high-side driver is supplied by a bootstrap voltage of a bootstrap node and a floating reference voltage of a floating reference node, which controls the high-side transistor to provide an input voltage to the floating reference node according to the set signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides a supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node according to a control voltage. The active diode includes a first-type well coupled to the bootstrap node, where the high-side driver is disposed.
Abstract translation: 适用于开关模式转换器的高边电路包括电平移位器，高侧驱动器，高侧晶体管，电容器和有源二极管。 电平移位器接收第一信号以产生设置信号。 高侧驱动器由自举节点的自举电压和浮动参考节点的浮动参考电压提供，其控制高侧晶体管，以根据设置的信号向浮动参考节点提供输入电压。 电容器耦合在引导节点和浮动参考节点之间。 有源二极管为引导节点提供电源电压。 当自举电压超过电源电压时，有源二极管根据控制电压隔离引导节点的电源电压。 有源二极管包括耦合到自举节点的第一类阱，其中设置了高侧驱动器。
-
公开(公告)号：US08723256B1
公开(公告)日：2014-05-13
申请号：US13670951
申请日：2012-11-07
Inventor： Wen-Cheng Lin , Shang-Hui Tu , Shin-Cheng Lin
IPC: H01L29/66
CPC classification number: H01L29/0847 , H01L29/0634 , H01L29/1045 , H01L29/42368 , H01L29/66659 , H01L29/7835
Abstract: A semiconductor device is provided. The device includes a semiconductor substrate and a gate structure thereon. A well region is formed in the semiconductor substrate. A drain region and a source region are respectively formed in the semiconductor substrate inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. The semiconductor substrate and the first heavily doped region have a first conductivity type and the well region and the second heavily doped region have a second conductivity type. A method for fabricating a semiconductor device is also disclosed.
Abstract translation: 提供半导体器件。 该器件包括半导体衬底及其上的栅极结构。 在半导体衬底中形成阱区。 漏极区域和源极区域分别形成在阱区域内部和外部的半导体衬底中。 在漏极区域和源极区域之间的阱区域中形成至少一组第一和第二重掺杂区域，其中第一和第二重掺杂区域从底部到顶部垂直堆叠并且具有较大的掺杂浓度 而不是井区。 半导体衬底和第一重掺杂区域具有第一导电类型，阱区和第二重掺杂区具有第二导电类型。 还公开了一种制造半导体器件的方法。
-
公开(公告)号：US11955522B2
公开(公告)日：2024-04-09
申请号：US16789682
申请日：2020-02-13
Inventor： Cheng-Wei Chou , Shin-Cheng Lin , Yung-Fong Lin
IPC: H01L29/778 , H01L21/02 , H01L21/285 , H01L23/29 , H01L23/31 , H01L29/20 , H01L29/205 , H01L29/40 , H01L29/45 , H01L29/66
CPC classification number: H01L29/408 , H01L21/0217 , H01L21/02186 , H01L21/28575 , H01L23/291 , H01L23/3192 , H01L29/2003 , H01L29/205 , H01L29/452 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a source structure, and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure are disposed on the passivation layer.
-
-
-
-
-
-
-
-
-
Search Results
66
records
(took 0.027 seconds)
