公开(公告)号：US20120200778A1

公开(公告)日：2012-08-09

申请号：US13447342

申请日：2012-04-16

Applicant: Vijay Kumar KODAVALLA ,  Deepak Kumar ARAVAPALLI

Inventor： Vijay Kumar KODAVALLA ,  Deepak Kumar ARAVAPALLI

IPC: H04N9/68

CPC classification number: H04N9/68 ,  G06T5/009 ,  G06T5/40 ,  G06T5/50 ,  G06T2207/10016 ,  G06T2207/10024

Abstract: System and method for dynamically and adaptively enhancing user chosen colors on a frame-by-frame basis of an incoming digital video signal using a saturation gain is disclosed. In one embodiment, a saturation 1D-histogram for each of the user chosen colors is formed using a substantially current video frame. Further, a saturation gain, adaptive to slow or fast moving image sequences, is dynamically computed for each of the user chosen colors of the substantially current video frame using the corresponding saturation 1D-histogram of the substantially current video frame and corresponding saturation 1D-histogram information and a saturation gain of a substantially previous video frame. Furthermore, which one of the dynamically computed saturation gains associated with the user chosen colors to be applied on a per-pixel basis is determined. The determined saturation gain is applied to saturation component on the per-pixel basis in the substantially current or next video frame.

Abstract translation: 公开了一种用于使用饱和增益在输入数字视频信号的逐帧基础上动态地和自适应地增强用户选择的颜色的系统和方法。 在一个实施例中，使用基本上当前的视频帧来形成每个用户选择的颜色的饱和1D直方图。 此外，使用基本上当前视频帧的对应的饱和1D直方图和相应的饱和1D直方图，动态地计算针对基本上当前视频帧的每个用户选择的颜色的适应于慢或快速运动图像序列的饱和增益 信息和基本上先前的视频帧的饱和增益。 此外，确定与以每像素为基础施加的用户选择的颜色相关联的动态计算的饱和增益中的哪一个。 所确定的饱和增益在基本上当前或下一个视频帧中以每像素为基础被施加到饱和分量。

公开(公告)号：US20160282921A1

公开(公告)日：2016-09-29

申请号：US14754475

申请日：2015-06-29

Applicant: Vijay Kumar KODAVALLA

Inventor： Vijay Kumar KODAVALLA

IPC: G06F1/32

CPC classification number: G06F1/324 ,  H03L7/10 ,  H03L7/18 ,  H04B15/02 ,  H04B2215/065 ,  Y02D10/126

Abstract: This disclosure relates generally to a host-peripheral interface, and more particularly to system and method for dynamically adjusting a low power clock frequency of a host device upon detecting coupling of a peripheral device to the host device. In one embodiment, a method is provided for dynamically adjusting a low power clock frequency of a host device. The method comprises dynamically determining an initial frequency of a low power clock of the host device at which a low power link between the host device and a peripheral device is operational, computing a low power clock frequency range of the host device based on the initial frequency of the low power clock, assessing the low power link in the low power clock frequency range, and adjusting the low power clock frequency to a typical frequency of the low power clock frequency range based on the assessment.

Abstract translation: 本公开一般涉及主机 - 外设接口，更具体地涉及用于在检测到外围设备耦合到主机设备时动态调整主机设备的低功率时钟频率的系统和方法。 在一个实施例中，提供了一种用于动态调整主机设备的低功率时钟频率的方法。 该方法包括动态地确定主机设备的低功率时钟的初始频率，在主机设备和外围设备之间的低功率链路可操作的初始频率，基于初始频率计算主机设备的低功率时钟频率范围 评估低功率时钟频率范围内的低功率链路，并根据评估将低功率时钟频率调整到低功率时钟频率范围的典型频率。

公开(公告)号：US20150278418A1

公开(公告)日：2015-10-01

申请号：US14283454

申请日：2014-05-21

Applicant: Vijay Kumar KODAVALLA

Inventor： Vijay Kumar KODAVALLA

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/14

Abstract: The present disclosure relates to methods and related systems and computer-readable mediums. The methods include receiving a design for a programmable logic device (PLD). The design includes a plurality of nodes. The method also includes modifying, via one or more hardware processors, the design to include a logic analyzer circuit. The logic analyzer circuit includes inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes. In addition, the method includes outputting the design to the PLD to program the PLD. The disclosure also relates a system comprising a user logic circuit, a logic analyzer circuit, and a memory.

Abstract translation: 本公开涉及方法和相关系统以及计算机可读介质。 这些方法包括接收可编程逻辑器件（PLD）的设计。 该设计包括多个节点。 该方法还包括通过一个或多个硬件处理器修改包括逻辑分析器电路的设计。 逻辑分析器电路包括用于多个可选择的捕获信号组的输入，用于连接到多个节点中的选定节点。 此外，该方法包括将设计输出到PLD以对PLD进行编程。 本公开还涉及包括用户逻辑电路，逻辑分析器电路和存储器的系统。

公开(公告)号：US20150278991A1

公开(公告)日：2015-10-01

申请号：US14283939

申请日：2014-05-21

Applicant: Vijay Kumar KODAVALLA

Inventor： Vijay Kumar KODAVALLA

IPC: G06T3/40 ,  G06T1/60

CPC classification number: G06T3/4023

Abstract: A method, system, and non-transitory computer-readable storage medium for image scaling is provided. In one embodiment, the method may include determining one or more filter phases based on a vertical target grid distance and a horizontal target grid distance; and scaling, by one or more hardware processors, an input image using filter coefficients corresponding to the one or more filters phases to output a target image. The horizontal target grid distance may be based on a ratio of a number of horizontal filter phases and a horizontal scaling ratio, and the vertical target grid distance may be based on a ratio of a number of vertical filter phases and a vertical scaling ratio.

Abstract translation: 提供了一种用于图像缩放的方法，系统和非暂时的计算机可读存储介质。 在一个实施例中，该方法可以包括基于垂直目标网格距离和水平目标网格距离来确定一个或多个滤波器相位; 以及使用与所述一个或多个滤波器相位对应的滤波器系数，通过一个或多个硬件处理器对输入图像进行缩放以输出目标图像。 水平目标网格距离可以基于多个水平滤波器相位和水平缩放比率的比率，并且垂直目标网格距离可以基于垂直滤波器相位数和垂直缩放比率的比率。