公开(公告)号：US06810482B1

公开(公告)日：2004-10-26

申请号：US09771322

申请日：2001-01-26

申请人： Vikram Saxena ,  Renu Mehra

发明人： Vikram Saxena ,  Renu Mehra

IPC分类号： G06F132

CPC分类号： G06F17/5022

摘要： The present invention facilitates relatively accurate power consumption estimates performed at the register transfer level for scaleable circuits with similar architectural characteristics and features. A power evaluation process of the present invention includes a critical path delay based macro energy model creation process and a scaleable power consumption estimation process. In one embodiment of the present invention, the critical path delay based macro energy model creation process provides a base macro energy table and scaling functions (e.g., a bit width scaling function and a normalizing period scaling function). The scaleable power consumption estimation process utilizes the base macro energy table and scaling functions to estimate power consumption of a circuit. The base energy macro table comprises energy values that are based upon a critical path delay period and correspond to normalized toggle rates. Different bit width circuit toggle rates are converted to normalized toggle rates based upon time periods derived from a normalizing period scaling function. The normalized rates are utilized to lookup an energy per event value that is then scaled in accordance with a bit width scaling function of the present invention. The bit width scaling function is a polynomial function based upon a least square error analysis of sample bit width power consumption values corresponding to average characteristic parameters multiplied by a critical path normalization value (e.g., 1.2 times the critical path delay). The scaled energy per event value is divided by the critical path normalization value to provide an power consumption estimate for a particular bit width.

摘要翻译： 本发明便于在具有相似结构特征和特征的可扩展电路的寄存器传送级别处执行的相对精确的功率消耗估计。 本发明的功率评估过程包括基于关键路径延迟的宏观能量模型创建过程和可缩放功耗估计过程。 在本发明的一个实施例中，基于关键路径延迟的宏能量模型创建过程提供基本宏能量表和缩放函数（例如，位宽缩放函数和归一化周期缩放函数）。 可扩展功耗估计过程利用基本宏能量表和缩放函数来估计电路的功耗。 基能量宏表包括基于关键路径延迟周期并对应于归一化切换速率的能量值。 基于归一化周期缩放函数导出的时间段，不同的位宽电路切换速率被转换为归一化的转换速率。 归一化速率用于查找每个事件值的能量，然后根据本发明的位宽度缩放函数对其进行缩放。 比特宽度缩放函数是基于对应于乘以关键路径归一化值（例如，关键路径延迟的1.2倍）的平均特征参数的采样比特宽度功耗值的最小平方误差分析的多项式函数。 每个事件值的缩放能量除以关键路径归一化值以提供特定位宽度的功耗估计。

公开(公告)号：US06038381A

公开(公告)日：2000-03-14

申请号：US977562

申请日：1997-11-25

申请人： Michael Munch ,  Bernd Wurth ,  Renu Mehra ,  James David Sproch

发明人： Michael Munch ,  Bernd Wurth ,  Renu Mehra ,  James David Sproch

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A computer-implemented process for determining a signal function for use in controlling the application of signal operands to a circuit-implemented function for the purpose of power reduction. The present invention receives a netlist represented as a graph data structure having nodes interconnected with signal lines. A node can have one output (single fan-out) or can have more than one output (multiple fan-outs). Termination points of the graph are identified as inputs to registers or primary outputs. From the termination points, and using a breadth-first traversal process, the present invention traverses each node of the netlist. A parent node is not processed in the breadth-first traversal until all of its child nodes have been processed. During traversal, an activation signal function is constructed for each input of a node. If the node has multiple outputs then a disjunctive Boolean expression is used, otherwise a conjunctive Boolean expression is used to determine the activation signal function. Activation signal circuitry is then added to each node if the power savings meet certain specified area and timing considerations. Selected nodes have operand isolation circuitry added thereto to implement the activation signal functions. The activation signal circuitry is used to gate the operand signal inputs to the node thereby saving power when the node's output is ignored.

摘要翻译： 用于确定信号功能的计算机实现的过程，用于控制信号操作数到电路实现的功能的应用以降低功率。 本发明接收表示为具有与信号线互连的节点的图形数据结构的网表。 一个节点可以有一个输出（单个扇出）或可以有多个输出（多个扇出）。 曲线图的终点被标识为寄存器或主输出的输入。 从终端点开始，使用宽度优先遍历处理，本发明遍历网表的每个节点。 在广度优先遍历之前不处理父节点，直到其所有子节点都被处理。 在遍历期间，为节点的每个输入构造激活信号功能。 如果节点具有多个输出，则使用分离布尔表达式，否则使用连接布尔表达式来确定激活信号函数。 如果功率节省满足某些特定的区域和时序考虑，则激活信号电路被添加到每个节点。 所选择的节点具有添加到其中的操作数隔离电路以实现激活信号功能。 激活信号电路用于将操作数信号输入选通到节点，从而在节点的输出被忽略时节省功率。

公开(公告)号：US06247134B1

公开(公告)日：2001-06-12

申请号：US09283128

申请日：1999-03-31

申请人： James D. Sproch ,  Michael Münch ,  Renu Mehra

发明人： James D. Sproch ,  Michael Münch ,  Renu Mehra

IPC分类号： G06F132

CPC分类号： G06F9/3869 ,  G06F1/3287 ,  G06F9/3832 ,  G06F9/3867 ,  Y02D10/171

摘要： A method and system for power savings within a pipelined design by performing intelligent stage gating. The present invention recognizes that not every operand applied to the input of a pipeline requires a recomputation in the different pipeline stages. Circuitry is used to generate a signal, C, indicating that this condition holds. C is then used to gate the register bank at the input of the first pipeline stage thereby potentially saving power in the register bank. Moreover, C can also be stored in a register, the output of which: a) gates the register bank of the second stage; and b) connects to another register to store signal C to be used in the third stage. Power savings is provided by not clocking the register circuit of the stage, and in some instances, power is saved within the stage's associated combinational logic. In one embodiment, a register (to store C) is added in each stage of a pipeline to use C as a gating signal in the subsequent stage. This yields a structure in which signal C propagates through the pipeline in synchronization with the clock, successively gating the associated register banks. The value of C is generated whenever the output of the stage is inconsequential. For example, the output can be inconsequential in cases when duplicate operands are received in back-to-back clock cycles. Also, in maximum and minimum cases a operand that is not larger or smaller, respectively, than the largest or smallest previously received operand can yield an inconsequential result.

摘要翻译： 通过执行智能阶段门控，在流水线设计中节能的方法和系统。 本发明认识到，不是应用于流水线的输入的每个操作数都不需要在不同的流水线级重新计算。 电路用于产生指示该条件成立的信号C。 C然后用于在第一流水线级的输入端对门限寄存器组进行门控，从而潜在地节省了寄存器组的功率。 此外，C也可以存储在寄存器中，其输出：a）门控第二级的寄存器组; 并且b）连接到另一寄存器以存储要在第三级中使用的信号C. 通过不对该级的寄存器电路进行计时来提供功率节省，并且在一些情况下，功率节省在该相​​关联的组合逻辑内。 在一个实施例中，在流水线的每个级中添加一个寄存器（存储C），以便在后续阶段使用C作为门控信号。 这产生了其中信号C与时钟同步地通过流水线传播的结构，连续地选通相关联的寄存器组。 只要阶段的输出无关紧要，就产生C的值。 例如，在背靠背时钟周期接收到重复操作数的情况下，输出可能无关紧要。 此外，在最大和最小情况下，分别不大于或小于最大或最小的先前接收的操作数的操作数可能产生无关紧要的结果。