公开(公告)号：US06810482B1

公开(公告)日：2004-10-26

申请号：US09771322

申请日：2001-01-26

申请人： Vikram Saxena ,  Renu Mehra

发明人： Vikram Saxena ,  Renu Mehra

IPC分类号： G06F132

CPC分类号： G06F17/5022

摘要： The present invention facilitates relatively accurate power consumption estimates performed at the register transfer level for scaleable circuits with similar architectural characteristics and features. A power evaluation process of the present invention includes a critical path delay based macro energy model creation process and a scaleable power consumption estimation process. In one embodiment of the present invention, the critical path delay based macro energy model creation process provides a base macro energy table and scaling functions (e.g., a bit width scaling function and a normalizing period scaling function). The scaleable power consumption estimation process utilizes the base macro energy table and scaling functions to estimate power consumption of a circuit. The base energy macro table comprises energy values that are based upon a critical path delay period and correspond to normalized toggle rates. Different bit width circuit toggle rates are converted to normalized toggle rates based upon time periods derived from a normalizing period scaling function. The normalized rates are utilized to lookup an energy per event value that is then scaled in accordance with a bit width scaling function of the present invention. The bit width scaling function is a polynomial function based upon a least square error analysis of sample bit width power consumption values corresponding to average characteristic parameters multiplied by a critical path normalization value (e.g., 1.2 times the critical path delay). The scaled energy per event value is divided by the critical path normalization value to provide an power consumption estimate for a particular bit width.

摘要翻译： 本发明便于在具有相似结构特征和特征的可扩展电路的寄存器传送级别处执行的相对精确的功率消耗估计。 本发明的功率评估过程包括基于关键路径延迟的宏观能量模型创建过程和可缩放功耗估计过程。 在本发明的一个实施例中，基于关键路径延迟的宏能量模型创建过程提供基本宏能量表和缩放函数（例如，位宽缩放函数和归一化周期缩放函数）。 可扩展功耗估计过程利用基本宏能量表和缩放函数来估计电路的功耗。 基能量宏表包括基于关键路径延迟周期并对应于归一化切换速率的能量值。 基于归一化周期缩放函数导出的时间段，不同的位宽电路切换速率被转换为归一化的转换速率。 归一化速率用于查找每个事件值的能量，然后根据本发明的位宽度缩放函数对其进行缩放。 比特宽度缩放函数是基于对应于乘以关键路径归一化值（例如，关键路径延迟的1.2倍）的平均特征参数的采样比特宽度功耗值的最小平方误差分析的多项式函数。 每个事件值的缩放能量除以关键路径归一化值以提供特定位宽度的功耗估计。

公开(公告)号：US20070005533A1

公开(公告)日：2007-01-04

申请号：US11120921

申请日：2005-05-02

申请人： Mahesh Iyer ,  Vikram Saxena

发明人： Mahesh Iyer ,  Vikram Saxena

IPC分类号： G06F15/18

CPC分类号： G06F17/504

摘要： Techniques are presented for identifying blockable subsets. Blockable subsets can increase the efficiency by which solutions to a constraint set representation (CSR) can be found. Nodes of a blockable subset can be marked as “blocked” and learning or implication procedures, used as part of a CSR solving process, can be designed to skip nodes marked as blocked. The identification of a particular blockable subset is typically associated with certain conditions being true. If and when the conditions no longer hold, the nodes of the blockable subset need to be unblocked. One type of blockable subset can be identified during the operation of an implication engine (IE) by a technique called justified node blocking (JNB). Another type of blockable subset can be identified by a technique called pivot node learning (PNL). PNL can be applied in-between application of an IE and application of case-based learning.

公开(公告)号：US09940352B1

公开(公告)日：2018-04-10

申请号：US14988596

申请日：2016-01-05

申请人： Rohit Satapathy ,  Sapeksha Vemulapati ,  Kapil Gupta ,  Vikram Saxena ,  Gaurav Mishra

发明人： Rohit Satapathy ,  Sapeksha Vemulapati ,  Kapil Gupta ,  Vikram Saxena ,  Gaurav Mishra

IPC分类号： G06F17/30

CPC分类号： G06F17/30424 ,  G06F17/30554 ,  G06F17/3056

摘要： Systems and methods are disclosed to enable delivering a contextually relevant action for an underlying focal point of a communication (an “entity”) between users over computing devices. Delivery of a contextually relevant action entails identifying the entity and associated descriptors or amplifying words in the communication surrounding the entity, reviewing databases of actions taken with respect to the identified entity and associated descriptors, reviewing the functions and features of platforms and applications supported on users' computing devices, computing correlations between the actions taken and entity involved and computing devices' available functions and features, and selecting a contextually relevant action from the computed correlation. The selected contextually relevant action is displayed simply as an executable action for a user to take or as a description of the entity or as a series of possible executable actions to take.

公开(公告)号：US07376939B1

公开(公告)日：2008-05-20

申请号：US10072212

申请日：2002-02-07

申请人： Anshuman Nayak ,  Malay Haldar ,  Alok Choudhary ,  Vikram Saxena ,  Prithviraj Banerjee

发明人： Anshuman Nayak ,  Malay Haldar ,  Alok Choudhary ,  Vikram Saxena ,  Prithviraj Banerjee

IPC分类号： G06F9/45 ,  G06F9/455 ,  G06F17/50 ,  G06F7/62 ,  G06F9/44

CPC分类号： G06F17/5045 ,  G06F17/5031

摘要： Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. Further, techniques are provided for modeling the timing behavior of a function or functional block without drawing a timing diagram; understanding the interface behavior of a function block which captures the timing waveforms; specifying virtual functions which are built using basic functional units and their timing behavior; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.

摘要翻译： 电子设计自动化工具规定了系统级及其组件（包括嵌入式处理器，算术逻辑单元（ALU），乘法器，分频器，嵌入式存储器元件，可编程逻辑单元等）的知识产权（IP）内核的架构。 指定IP内核及其接口; 并通过其界面了解IP内核和功能。 此外，提供了用于对功能或功能块的定时行为建模而不绘制时序图的技术; 了解捕获时序波形的功能块的接口行为; 指定使用基本功能单元构建的虚拟功能及其时序行为; 解析和创建用于分析编译规范的内部图形表单; 匹配架构规范中的组件及其实例化以映射从应用程序生成的输入图中的计算; 并将规范映射到目标的组件上。

公开(公告)号：US07353216B2

公开(公告)日：2008-04-01

申请号：US11120921

申请日：2005-05-02

申请人： Mahesh Anantharaman Iyer ,  Vikram Saxena

发明人： Mahesh Anantharaman Iyer ,  Vikram Saxena

IPC分类号： G06F17/00 ,  G06N5/02

CPC分类号： G06F17/504

摘要： Techniques are presented for identifying blockable subsets. Blockable subsets can increase the efficiency by which solutions to a constraint set representation (CSR) can be found. Nodes of a blockable subset can be marked as “blocked” and learning or implication procedures, used as part of a CSR solving process, can be designed to skip nodes marked as blocked. The identification of a particular blockable subset is typically associated with certain conditions being true. If and when the conditions no longer hold, the nodes of the blockable subset need to be unblocked. One type of blockable subset can be identified during the operation of an implication engine (IE) by a technique called justified node blocking (JNB). Another type of blockable subset can be identified by a technique called pivot node learning (PNL). PNL can be applied in-between application of an IE and application of case-based learning.

摘要翻译： 提出了用于识别可阻塞子集的技术。 可阻止的子集可以提高可以找到约束集表示（CSR）的解决方案的效率。 可阻塞子集的节点可以被标记为“阻止”，并且用作CSR解决过程的一部分的学习或含义过程可被设计为跳过标记为被阻止的节点。 特定可阻挡子集的识别通常与某些条件成立相关联。 如果条件不再保持，则可阻止子集的节点需要被解除阻塞。 可以通过称为对称节点阻塞（JNB）的技术在隐含引擎（IE）的操作期间识别一种类型的可阻止子集。 可以通过称为枢轴节点学习（PNL）的技术来识别另一种类型的可阻止子集。 PNL可以应用于IE的应用和基于案例的学习的应用。